i8254xGBe.hh (11263:8dcc6b40f164) | i8254xGBe.hh (11320:42ecb523c64a) |
---|---|
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 400 unchanged lines hidden (view full) --- 409 long descLen() const override { return igbe->regs.tdlen() >> 4; } 410 void updateHead(long h) override { igbe->regs.tdh(h); } 411 void enableSm() override; 412 void actionAfterWb() override; 413 void fetchAfterWb() override { 414 if (!igbe->txTick && igbe->drainState() == DrainState::Running) 415 fetchDescriptors(); 416 } | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 400 unchanged lines hidden (view full) --- 409 long descLen() const override { return igbe->regs.tdlen() >> 4; } 410 void updateHead(long h) override { igbe->regs.tdh(h); } 411 void enableSm() override; 412 void actionAfterWb() override; 413 void fetchAfterWb() override { 414 if (!igbe->txTick && igbe->drainState() == DrainState::Running) 415 fetchDescriptors(); 416 } |
417 | |
418 419 | 417 418 |
419 |
|
420 bool pktDone; 421 bool isTcp; 422 bool pktWaiting; 423 bool pktMultiDesc; 424 Addr completionAddress; 425 bool completionEnabled; 426 uint32_t descEnd; | 420 bool pktDone; 421 bool isTcp; 422 bool pktWaiting; 423 bool pktMultiDesc; 424 Addr completionAddress; 425 bool completionEnabled; 426 uint32_t descEnd; |
427 | |
428 | 427 |
428 |
|
429 // tso variables 430 bool useTso; 431 Addr tsoHeaderLen; 432 Addr tsoMss; 433 Addr tsoTotalLen; 434 Addr tsoUsedLen; 435 Addr tsoPrevSeq; 436 Addr tsoPktPayloadBytes; --- 49 unchanged lines hidden (view full) --- 486 EventWrapper<TxDescCache, &TxDescCache::pktComplete> pktEvent; 487 488 void headerComplete(); 489 EventWrapper<TxDescCache, &TxDescCache::headerComplete> headerEvent; 490 491 492 void completionWriteback(Addr a, bool enabled) { 493 DPRINTF(EthernetDesc, | 429 // tso variables 430 bool useTso; 431 Addr tsoHeaderLen; 432 Addr tsoMss; 433 Addr tsoTotalLen; 434 Addr tsoUsedLen; 435 Addr tsoPrevSeq; 436 Addr tsoPktPayloadBytes; --- 49 unchanged lines hidden (view full) --- 486 EventWrapper<TxDescCache, &TxDescCache::pktComplete> pktEvent; 487 488 void headerComplete(); 489 EventWrapper<TxDescCache, &TxDescCache::headerComplete> headerEvent; 490 491 492 void completionWriteback(Addr a, bool enabled) { 493 DPRINTF(EthernetDesc, |
494 "Completion writeback Addr: %#x enabled: %d\n", | 494 "Completion writeback Addr: %#x enabled: %d\n", |
495 a, enabled); 496 completionAddress = a; 497 completionEnabled = enabled; 498 } 499 500 bool hasOutstandingEvents() override; 501 502 void nullCallback() { --- 58 unchanged lines hidden --- | 495 a, enabled); 496 completionAddress = a; 497 completionEnabled = enabled; 498 } 499 500 bool hasOutstandingEvents() override; 501 502 void nullCallback() { --- 58 unchanged lines hidden --- |