i8254xGBe.cc (12963:214e39f63149) i8254xGBe.cc (13342:1ddb43f47325)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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189
190 //
191 // Handle read of register here
192 //
193
194
195 switch (daddr) {
196 case REG_CTRL:
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 180 unchanged lines hidden (view full) ---

189
190 //
191 // Handle read of register here
192 //
193
194
195 switch (daddr) {
196 case REG_CTRL:
197 pkt->set(regs.ctrl());
197 pkt->setLE<uint32_t>(regs.ctrl());
198 break;
199 case REG_STATUS:
198 break;
199 case REG_STATUS:
200 pkt->set(regs.sts());
200 pkt->setLE<uint32_t>(regs.sts());
201 break;
202 case REG_EECD:
201 break;
202 case REG_EECD:
203 pkt->set(regs.eecd());
203 pkt->setLE<uint32_t>(regs.eecd());
204 break;
205 case REG_EERD:
204 break;
205 case REG_EERD:
206 pkt->set(regs.eerd());
206 pkt->setLE<uint32_t>(regs.eerd());
207 break;
208 case REG_CTRL_EXT:
207 break;
208 case REG_CTRL_EXT:
209 pkt->set(regs.ctrl_ext());
209 pkt->setLE<uint32_t>(regs.ctrl_ext());
210 break;
211 case REG_MDIC:
210 break;
211 case REG_MDIC:
212 pkt->set(regs.mdic());
212 pkt->setLE<uint32_t>(regs.mdic());
213 break;
214 case REG_ICR:
215 DPRINTF(Ethernet, "Reading ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n",
216 regs.icr(), regs.imr, regs.iam, regs.ctrl_ext.iame());
213 break;
214 case REG_ICR:
215 DPRINTF(Ethernet, "Reading ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n",
216 regs.icr(), regs.imr, regs.iam, regs.ctrl_ext.iame());
217 pkt->set(regs.icr());
217 pkt->setLE<uint32_t>(regs.icr());
218 if (regs.icr.int_assert() || regs.imr == 0) {
219 regs.icr = regs.icr() & ~mask(30);
220 DPRINTF(Ethernet, "Cleared ICR. ICR=%#x\n", regs.icr());
221 }
222 if (regs.ctrl_ext.iame() && regs.icr.int_assert())
223 regs.imr &= ~regs.iam;
224 chkInterrupt();
225 break;
226 case REG_EICR:
227 // This is only useful for MSI, but the driver reads it every time
228 // Just don't do anything
218 if (regs.icr.int_assert() || regs.imr == 0) {
219 regs.icr = regs.icr() & ~mask(30);
220 DPRINTF(Ethernet, "Cleared ICR. ICR=%#x\n", regs.icr());
221 }
222 if (regs.ctrl_ext.iame() && regs.icr.int_assert())
223 regs.imr &= ~regs.iam;
224 chkInterrupt();
225 break;
226 case REG_EICR:
227 // This is only useful for MSI, but the driver reads it every time
228 // Just don't do anything
229 pkt->set(0);
229 pkt->setLE<uint32_t>(0);
230 break;
231 case REG_ITR:
230 break;
231 case REG_ITR:
232 pkt->set(regs.itr());
232 pkt->setLE<uint32_t>(regs.itr());
233 break;
234 case REG_RCTL:
233 break;
234 case REG_RCTL:
235 pkt->set(regs.rctl());
235 pkt->setLE<uint32_t>(regs.rctl());
236 break;
237 case REG_FCTTV:
236 break;
237 case REG_FCTTV:
238 pkt->set(regs.fcttv());
238 pkt->setLE<uint32_t>(regs.fcttv());
239 break;
240 case REG_TCTL:
239 break;
240 case REG_TCTL:
241 pkt->set(regs.tctl());
241 pkt->setLE<uint32_t>(regs.tctl());
242 break;
243 case REG_PBA:
242 break;
243 case REG_PBA:
244 pkt->set(regs.pba());
244 pkt->setLE<uint32_t>(regs.pba());
245 break;
246 case REG_WUC:
247 case REG_WUFC:
248 case REG_WUS:
249 case REG_LEDCTL:
245 break;
246 case REG_WUC:
247 case REG_WUFC:
248 case REG_WUS:
249 case REG_LEDCTL:
250 pkt->set(0); // We don't care, so just return 0
250 pkt->setLE<uint32_t>(0); // We don't care, so just return 0
251 break;
252 case REG_FCRTL:
251 break;
252 case REG_FCRTL:
253 pkt->set(regs.fcrtl());
253 pkt->setLE<uint32_t>(regs.fcrtl());
254 break;
255 case REG_FCRTH:
254 break;
255 case REG_FCRTH:
256 pkt->set(regs.fcrth());
256 pkt->setLE<uint32_t>(regs.fcrth());
257 break;
258 case REG_RDBAL:
257 break;
258 case REG_RDBAL:
259 pkt->set(regs.rdba.rdbal());
259 pkt->setLE<uint32_t>(regs.rdba.rdbal());
260 break;
261 case REG_RDBAH:
260 break;
261 case REG_RDBAH:
262 pkt->set(regs.rdba.rdbah());
262 pkt->setLE<uint32_t>(regs.rdba.rdbah());
263 break;
264 case REG_RDLEN:
263 break;
264 case REG_RDLEN:
265 pkt->set(regs.rdlen());
265 pkt->setLE<uint32_t>(regs.rdlen());
266 break;
267 case REG_SRRCTL:
266 break;
267 case REG_SRRCTL:
268 pkt->set(regs.srrctl());
268 pkt->setLE<uint32_t>(regs.srrctl());
269 break;
270 case REG_RDH:
269 break;
270 case REG_RDH:
271 pkt->set(regs.rdh());
271 pkt->setLE<uint32_t>(regs.rdh());
272 break;
273 case REG_RDT:
272 break;
273 case REG_RDT:
274 pkt->set(regs.rdt());
274 pkt->setLE<uint32_t>(regs.rdt());
275 break;
276 case REG_RDTR:
275 break;
276 case REG_RDTR:
277 pkt->set(regs.rdtr());
277 pkt->setLE<uint32_t>(regs.rdtr());
278 if (regs.rdtr.fpd()) {
279 rxDescCache.writeback(0);
280 DPRINTF(EthernetIntr,
281 "Posting interrupt because of RDTR.FPD write\n");
282 postInterrupt(IT_RXT);
283 regs.rdtr.fpd(0);
284 }
285 break;
286 case REG_RXDCTL:
278 if (regs.rdtr.fpd()) {
279 rxDescCache.writeback(0);
280 DPRINTF(EthernetIntr,
281 "Posting interrupt because of RDTR.FPD write\n");
282 postInterrupt(IT_RXT);
283 regs.rdtr.fpd(0);
284 }
285 break;
286 case REG_RXDCTL:
287 pkt->set(regs.rxdctl());
287 pkt->setLE<uint32_t>(regs.rxdctl());
288 break;
289 case REG_RADV:
288 break;
289 case REG_RADV:
290 pkt->set(regs.radv());
290 pkt->setLE<uint32_t>(regs.radv());
291 break;
292 case REG_TDBAL:
291 break;
292 case REG_TDBAL:
293 pkt->set(regs.tdba.tdbal());
293 pkt->setLE<uint32_t>(regs.tdba.tdbal());
294 break;
295 case REG_TDBAH:
294 break;
295 case REG_TDBAH:
296 pkt->set(regs.tdba.tdbah());
296 pkt->setLE<uint32_t>(regs.tdba.tdbah());
297 break;
298 case REG_TDLEN:
297 break;
298 case REG_TDLEN:
299 pkt->set(regs.tdlen());
299 pkt->setLE<uint32_t>(regs.tdlen());
300 break;
301 case REG_TDH:
300 break;
301 case REG_TDH:
302 pkt->set(regs.tdh());
302 pkt->setLE<uint32_t>(regs.tdh());
303 break;
304 case REG_TXDCA_CTL:
303 break;
304 case REG_TXDCA_CTL:
305 pkt->set(regs.txdca_ctl());
305 pkt->setLE<uint32_t>(regs.txdca_ctl());
306 break;
307 case REG_TDT:
306 break;
307 case REG_TDT:
308 pkt->set(regs.tdt());
308 pkt->setLE<uint32_t>(regs.tdt());
309 break;
310 case REG_TIDV:
309 break;
310 case REG_TIDV:
311 pkt->set(regs.tidv());
311 pkt->setLE<uint32_t>(regs.tidv());
312 break;
313 case REG_TXDCTL:
312 break;
313 case REG_TXDCTL:
314 pkt->set(regs.txdctl());
314 pkt->setLE<uint32_t>(regs.txdctl());
315 break;
316 case REG_TADV:
315 break;
316 case REG_TADV:
317 pkt->set(regs.tadv());
317 pkt->setLE<uint32_t>(regs.tadv());
318 break;
319 case REG_TDWBAL:
318 break;
319 case REG_TDWBAL:
320 pkt->set(regs.tdwba & mask(32));
320 pkt->setLE<uint32_t>(regs.tdwba & mask(32));
321 break;
322 case REG_TDWBAH:
321 break;
322 case REG_TDWBAH:
323 pkt->set(regs.tdwba >> 32);
323 pkt->setLE<uint32_t>(regs.tdwba >> 32);
324 break;
325 case REG_RXCSUM:
324 break;
325 case REG_RXCSUM:
326 pkt->set(regs.rxcsum());
326 pkt->setLE<uint32_t>(regs.rxcsum());
327 break;
328 case REG_RLPML:
327 break;
328 case REG_RLPML:
329 pkt->set(regs.rlpml);
329 pkt->setLE<uint32_t>(regs.rlpml);
330 break;
331 case REG_RFCTL:
330 break;
331 case REG_RFCTL:
332 pkt->set(regs.rfctl());
332 pkt->setLE<uint32_t>(regs.rfctl());
333 break;
334 case REG_MANC:
333 break;
334 case REG_MANC:
335 pkt->set(regs.manc());
335 pkt->setLE<uint32_t>(regs.manc());
336 break;
337 case REG_SWSM:
336 break;
337 case REG_SWSM:
338 pkt->set(regs.swsm());
338 pkt->setLE<uint32_t>(regs.swsm());
339 regs.swsm.smbi(1);
340 break;
341 case REG_FWSM:
339 regs.swsm.smbi(1);
340 break;
341 case REG_FWSM:
342 pkt->set(regs.fwsm());
342 pkt->setLE<uint32_t>(regs.fwsm());
343 break;
344 case REG_SWFWSYNC:
343 break;
344 case REG_SWFWSYNC:
345 pkt->set(regs.sw_fw_sync);
345 pkt->setLE<uint32_t>(regs.sw_fw_sync);
346 break;
347 default:
348 if (!IN_RANGE(daddr, REG_VFTA, VLAN_FILTER_TABLE_SIZE*4) &&
349 !IN_RANGE(daddr, REG_RAL, RCV_ADDRESS_TABLE_SIZE*8) &&
350 !IN_RANGE(daddr, REG_MTA, MULTICAST_TABLE_SIZE*4) &&
351 !IN_RANGE(daddr, REG_CRCERRS, STATS_REGS_SIZE))
352 panic("Read request to unknown register number: %#x\n", daddr);
353 else
346 break;
347 default:
348 if (!IN_RANGE(daddr, REG_VFTA, VLAN_FILTER_TABLE_SIZE*4) &&
349 !IN_RANGE(daddr, REG_RAL, RCV_ADDRESS_TABLE_SIZE*8) &&
350 !IN_RANGE(daddr, REG_MTA, MULTICAST_TABLE_SIZE*4) &&
351 !IN_RANGE(daddr, REG_CRCERRS, STATS_REGS_SIZE))
352 panic("Read request to unknown register number: %#x\n", daddr);
353 else
354 pkt->set(0);
354 pkt->setLE<uint32_t>(0);
355 };
356
357 pkt->makeAtomicResponse();
358 return pioDelay;
359}
360
361Tick
362IGbE::write(PacketPtr pkt)

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370
371 // Only Memory register BAR is allowed
372 assert(bar == 0);
373
374 // Only 32bit accesses allowed
375 assert(pkt->getSize() == sizeof(uint32_t));
376
377 DPRINTF(Ethernet, "Wrote device register %#X value %#X\n",
355 };
356
357 pkt->makeAtomicResponse();
358 return pioDelay;
359}
360
361Tick
362IGbE::write(PacketPtr pkt)

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370
371 // Only Memory register BAR is allowed
372 assert(bar == 0);
373
374 // Only 32bit accesses allowed
375 assert(pkt->getSize() == sizeof(uint32_t));
376
377 DPRINTF(Ethernet, "Wrote device register %#X value %#X\n",
378 daddr, pkt->get());
378 daddr, pkt->getLE<uint32_t>());
379
380 //
381 // Handle write of register here
382 //
379
380 //
381 // Handle write of register here
382 //
383 uint32_t val = pkt->get();
383 uint32_t val = pkt->getLE<uint32_t>();
384
385 Regs::RCTL oldrctl;
386 Regs::TCTL oldtctl;
387
388 switch (daddr) {
389 case REG_CTRL:
390 regs.ctrl = val;
391 if (regs.ctrl.tfce())

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385 Regs::RCTL oldrctl;
386 Regs::TCTL oldtctl;
387
388 switch (daddr) {
389 case REG_CTRL:
390 regs.ctrl = val;
391 if (regs.ctrl.tfce())

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