1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 50 unchanged lines hidden (view full) --- 59 60IGbE::IGbE(const Params *p) 61 : EtherDevice(p), etherInt(NULL), cpa(NULL), 62 rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), inTick(false), 63 rxTick(false), txTick(false), txFifoTick(false), rxDmaPacket(false), 64 pktOffset(0), fetchDelay(p->fetch_delay), wbDelay(p->wb_delay), 65 fetchCompDelay(p->fetch_comp_delay), wbCompDelay(p->wb_comp_delay), 66 rxWriteDelay(p->rx_write_delay), txReadDelay(p->tx_read_delay), |
67 rdtrEvent([this]{ rdtrProcess(); }, name()), 68 radvEvent([this]{ radvProcess(); }, name()), 69 tadvEvent([this]{ tadvProcess(); }, name()), 70 tidvEvent([this]{ tidvProcess(); }, name()), 71 tickEvent([this]{ tick(); }, name()), 72 interEvent([this]{ delayIntEvent(); }, name()), |
73 rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size), 74 txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size), 75 lastInterrupt(0) 76{ 77 etherInt = new IGbEInt(name() + ".int", this); 78 79 // Initialized internal registers per Intel documentation 80 // All registers intialized to 0 by per register constructor --- 743 unchanged lines hidden (view full) --- 824 825 826///////////////////////////// IGbE::DescCache ////////////////////////////// 827 828template<class T> 829IGbE::DescCache<T>::DescCache(IGbE *i, const std::string n, int s) 830 : igbe(i), _name(n), cachePnt(0), size(s), curFetching(0), 831 wbOut(0), moreToWb(false), wbAlignment(0), pktPtr(NULL), |
832 wbDelayEvent([this]{ writeback1(); }, n), 833 fetchDelayEvent([this]{ fetchDescriptors1(); }, n), 834 fetchEvent([this]{ fetchComplete(); }, n), 835 wbEvent([this]{ wbComplete(); }, n) |
836{ 837 fetchBuf = new T[size]; 838 wbBuf = new T[size]; 839} 840 841template<class T> 842IGbE::DescCache<T>::~DescCache() 843{ --- 354 unchanged lines hidden (view full) --- 1198 1199 1200} 1201 1202///////////////////////////// IGbE::RxDescCache ////////////////////////////// 1203 1204IGbE::RxDescCache::RxDescCache(IGbE *i, const std::string n, int s) 1205 : DescCache<RxDesc>(i, n, s), pktDone(false), splitCount(0), |
1206 pktEvent([this]{ pktComplete(); }, n), 1207 pktHdrEvent([this]{ pktSplitDone(); }, n), 1208 pktDataEvent([this]{ pktSplitDone(); }, n) |
1209 1210{ 1211 annSmFetch = "RX Desc Fetch"; 1212 annSmWb = "RX Desc Writeback"; 1213 annUnusedDescQ = "RX Unused Descriptors"; 1214 annUnusedCacheQ = "RX Unused Descriptor Cache"; 1215 annUsedCacheQ = "RX Used Descriptor Cache"; 1216 annUsedDescQ = "RX Used Descriptors"; --- 335 unchanged lines hidden (view full) --- 1552 1553IGbE::TxDescCache::TxDescCache(IGbE *i, const std::string n, int s) 1554 : DescCache<TxDesc>(i,n, s), pktDone(false), isTcp(false), 1555 pktWaiting(false), pktMultiDesc(false), 1556 completionAddress(0), completionEnabled(false), 1557 useTso(false), tsoHeaderLen(0), tsoMss(0), tsoTotalLen(0), tsoUsedLen(0), 1558 tsoPrevSeq(0), tsoPktPayloadBytes(0), tsoLoadedHeader(false), 1559 tsoPktHasHeader(false), tsoDescBytesUsed(0), tsoCopyBytes(0), tsoPkts(0), |
1560 pktEvent([this]{ pktComplete(); }, n), 1561 headerEvent([this]{ headerComplete(); }, n), 1562 nullEvent([this]{ nullCallback(); }, n) |
1563{ 1564 annSmFetch = "TX Desc Fetch"; 1565 annSmWb = "TX Desc Writeback"; 1566 annUnusedDescQ = "TX Unused Descriptors"; 1567 annUnusedCacheQ = "TX Unused Descriptor Cache"; 1568 annUsedCacheQ = "TX Used Descriptor Cache"; 1569 annUsedDescQ = "TX Used Descriptors"; 1570 annDescQ = "TX Descriptors"; --- 1015 unchanged lines hidden --- |