1# Copyright (c) 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Nathan Binkert
40
| 1# Copyright (c) 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Nathan Binkert
40
|
| 41from m5.defines import buildEnv
|
41from m5.SimObject import SimObject
42from m5.params import *
43from m5.proxy import *
44from PciDevice import PciDevice
45
46class EtherObject(SimObject):
47 type = 'EtherObject'
48 abstract = True
49 cxx_header = "dev/net/etherobject.hh"
50
51class EtherLink(EtherObject):
52 type = 'EtherLink'
53 cxx_header = "dev/net/etherlink.hh"
54 int0 = SlavePort("interface 0")
55 int1 = SlavePort("interface 1")
56 delay = Param.Latency('0us', "packet transmit delay")
57 delay_var = Param.Latency('0ns', "packet transmit delay variability")
58 speed = Param.NetworkBandwidth('1Gbps', "link speed")
59 dump = Param.EtherDump(NULL, "dump object")
60
61class DistEtherLink(EtherObject):
62 type = 'DistEtherLink'
63 cxx_header = "dev/net/dist_etherlink.hh"
64 int0 = SlavePort("interface 0")
65 delay = Param.Latency('0us', "packet transmit delay")
66 delay_var = Param.Latency('0ns', "packet transmit delay variability")
67 speed = Param.NetworkBandwidth('1Gbps', "link speed")
68 dump = Param.EtherDump(NULL, "dump object")
69 dist_rank = Param.UInt32('0', "Rank of this gem5 process (dist run)")
70 dist_size = Param.UInt32('1', "Number of gem5 processes (dist run)")
71 sync_start = Param.Latency('5200000000000t', "first dist sync barrier")
72 sync_repeat = Param.Latency('10us', "dist sync barrier repeat")
73 server_name = Param.String('localhost', "Message server name")
74 server_port = Param.UInt32('2200', "Message server port")
75 is_switch = Param.Bool(False, "true if this a link in etherswitch")
76 dist_sync_on_pseudo_op = Param.Bool(False, "Start sync with pseudo_op")
77 num_nodes = Param.UInt32('2', "Number of simulate nodes")
78
79class EtherBus(EtherObject):
80 type = 'EtherBus'
81 cxx_header = "dev/net/etherbus.hh"
82 loopback = Param.Bool(True, "send packet back to the sending interface")
83 dump = Param.EtherDump(NULL, "dump object")
84 speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
85
86class EtherSwitch(EtherObject):
87 type = 'EtherSwitch'
88 cxx_header = "dev/net/etherswitch.hh"
89 dump = Param.EtherDump(NULL, "dump object")
90 fabric_speed = Param.NetworkBandwidth('10Gbps', "switch fabric speed in bits "
91 "per second")
92 interface = VectorMasterPort("Ethernet Interface")
93 output_buffer_size = Param.MemorySize('1MB', "size of output port buffers")
94 delay = Param.Latency('0us', "packet transmit delay")
95 delay_var = Param.Latency('0ns', "packet transmit delay variability")
96 time_to_live = Param.Latency('10ms', "time to live of MAC address maping")
97
98class EtherTapBase(EtherObject):
99 type = 'EtherTapBase'
100 abstract = True
101 cxx_header = "dev/net/ethertap.hh"
102 bufsz = Param.Int(10000, "tap buffer size")
103 dump = Param.EtherDump(NULL, "dump object")
104 tap = SlavePort("Ethernet interface to connect to gem5's network")
105
| 42from m5.SimObject import SimObject
43from m5.params import *
44from m5.proxy import *
45from PciDevice import PciDevice
46
47class EtherObject(SimObject):
48 type = 'EtherObject'
49 abstract = True
50 cxx_header = "dev/net/etherobject.hh"
51
52class EtherLink(EtherObject):
53 type = 'EtherLink'
54 cxx_header = "dev/net/etherlink.hh"
55 int0 = SlavePort("interface 0")
56 int1 = SlavePort("interface 1")
57 delay = Param.Latency('0us', "packet transmit delay")
58 delay_var = Param.Latency('0ns', "packet transmit delay variability")
59 speed = Param.NetworkBandwidth('1Gbps', "link speed")
60 dump = Param.EtherDump(NULL, "dump object")
61
62class DistEtherLink(EtherObject):
63 type = 'DistEtherLink'
64 cxx_header = "dev/net/dist_etherlink.hh"
65 int0 = SlavePort("interface 0")
66 delay = Param.Latency('0us', "packet transmit delay")
67 delay_var = Param.Latency('0ns', "packet transmit delay variability")
68 speed = Param.NetworkBandwidth('1Gbps', "link speed")
69 dump = Param.EtherDump(NULL, "dump object")
70 dist_rank = Param.UInt32('0', "Rank of this gem5 process (dist run)")
71 dist_size = Param.UInt32('1', "Number of gem5 processes (dist run)")
72 sync_start = Param.Latency('5200000000000t', "first dist sync barrier")
73 sync_repeat = Param.Latency('10us', "dist sync barrier repeat")
74 server_name = Param.String('localhost', "Message server name")
75 server_port = Param.UInt32('2200', "Message server port")
76 is_switch = Param.Bool(False, "true if this a link in etherswitch")
77 dist_sync_on_pseudo_op = Param.Bool(False, "Start sync with pseudo_op")
78 num_nodes = Param.UInt32('2', "Number of simulate nodes")
79
80class EtherBus(EtherObject):
81 type = 'EtherBus'
82 cxx_header = "dev/net/etherbus.hh"
83 loopback = Param.Bool(True, "send packet back to the sending interface")
84 dump = Param.EtherDump(NULL, "dump object")
85 speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
86
87class EtherSwitch(EtherObject):
88 type = 'EtherSwitch'
89 cxx_header = "dev/net/etherswitch.hh"
90 dump = Param.EtherDump(NULL, "dump object")
91 fabric_speed = Param.NetworkBandwidth('10Gbps', "switch fabric speed in bits "
92 "per second")
93 interface = VectorMasterPort("Ethernet Interface")
94 output_buffer_size = Param.MemorySize('1MB', "size of output port buffers")
95 delay = Param.Latency('0us', "packet transmit delay")
96 delay_var = Param.Latency('0ns', "packet transmit delay variability")
97 time_to_live = Param.Latency('10ms', "time to live of MAC address maping")
98
99class EtherTapBase(EtherObject):
100 type = 'EtherTapBase'
101 abstract = True
102 cxx_header = "dev/net/ethertap.hh"
103 bufsz = Param.Int(10000, "tap buffer size")
104 dump = Param.EtherDump(NULL, "dump object")
105 tap = SlavePort("Ethernet interface to connect to gem5's network")
106
|
| 107if buildEnv['USE_TUNTAP']:
108 class EtherTap(EtherTapBase):
109 type = 'EtherTap'
110 cxx_header = "dev/net/ethertap.hh"
111 tun_clone_device = Param.String('/dev/net/tun',
112 "Path to the tun clone device node")
113 tap_device_name = Param.String('gem5-tap', "Tap device name")
114
|
106class EtherTapStub(EtherTapBase):
107 type = 'EtherTapStub'
108 cxx_header = "dev/net/ethertap.hh"
109 port = Param.UInt16(3500, "Port helper should send packets to")
110
111class EtherDump(SimObject):
112 type = 'EtherDump'
113 cxx_header = "dev/net/etherdump.hh"
114 file = Param.String("dump file")
115 maxlen = Param.Int(96, "max portion of packet data to dump")
116
117class EtherDevice(PciDevice):
118 type = 'EtherDevice'
119 abstract = True
120 cxx_header = "dev/net/etherdevice.hh"
121 interface = MasterPort("Ethernet Interface")
122
123class IGbE(EtherDevice):
124 # Base class for two IGbE adapters listed above
125 type = 'IGbE'
126 cxx_header = "dev/net/i8254xGBe.hh"
127 hardware_address = Param.EthernetAddr(NextEthernetAddr,
128 "Ethernet Hardware Address")
129 rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
130 tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
131 rx_desc_cache_size = Param.Int(64,
132 "Number of enteries in the rx descriptor cache")
133 tx_desc_cache_size = Param.Int(64,
134 "Number of enteries in the rx descriptor cache")
135 VendorID = 0x8086
136 SubsystemID = 0x1008
137 SubsystemVendorID = 0x8086
138 Status = 0x0000
139 SubClassCode = 0x00
140 ClassCode = 0x02
141 ProgIF = 0x00
142 BAR0 = 0x00000000
143 BAR1 = 0x00000000
144 BAR2 = 0x00000000
145 BAR3 = 0x00000000
146 BAR4 = 0x00000000
147 BAR5 = 0x00000000
148 MaximumLatency = 0x00
149 MinimumGrant = 0xff
150 InterruptLine = 0x1e
151 InterruptPin = 0x01
152 BAR0Size = '128kB'
153 wb_delay = Param.Latency('10ns', "delay before desc writeback occurs")
154 fetch_delay = Param.Latency('10ns', "delay before desc fetch occurs")
155 fetch_comp_delay = Param.Latency('10ns', "delay after desc fetch occurs")
156 wb_comp_delay = Param.Latency('10ns', "delay after desc wb occurs")
157 tx_read_delay = Param.Latency('0ns', "delay after tx dma read")
158 rx_write_delay = Param.Latency('0ns', "delay after rx dma read")
159 phy_pid = Param.UInt16("Phy PID that corresponds to device ID")
160 phy_epid = Param.UInt16("Phy EPID that corresponds to device ID")
161
162class IGbE_e1000(IGbE):
163 # Older Intel 8254x based gigabit ethernet adapter
164 # Uses Intel e1000 driver
165 DeviceID = 0x1075
166 phy_pid = 0x02A8
167 phy_epid = 0x0380
168
169class IGbE_igb(IGbE):
170 # Newer Intel 8257x based gigabit ethernet adapter
171 # Uses Intel igb driver and in theory supports packet splitting and LRO
172 DeviceID = 0x10C9
173 phy_pid = 0x0141
174 phy_epid = 0x0CC0
175
176class EtherDevBase(EtherDevice):
177 type = 'EtherDevBase'
178 abstract = True
179 cxx_header = "dev/net/etherdevice.hh"
180
181 hardware_address = Param.EthernetAddr(NextEthernetAddr,
182 "Ethernet Hardware Address")
183
184 dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
185 dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
186 dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
187 dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
188
189 rx_delay = Param.Latency('1us', "Receive Delay")
190 tx_delay = Param.Latency('1us', "Transmit Delay")
191 rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo")
192 tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo")
193
194 rx_filter = Param.Bool(True, "Enable Receive Filter")
195 intr_delay = Param.Latency('10us', "Interrupt propagation delay")
196 rx_thread = Param.Bool(False, "dedicated kernel thread for transmit")
197 tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
198 rss = Param.Bool(False, "Receive Side Scaling")
199
200class NSGigE(EtherDevBase):
201 type = 'NSGigE'
202 cxx_header = "dev/net/ns_gige.hh"
203
204 dma_data_free = Param.Bool(False, "DMA of Data is free")
205 dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
206 dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
207
208 VendorID = 0x100B
209 DeviceID = 0x0022
210 Status = 0x0290
211 SubClassCode = 0x00
212 ClassCode = 0x02
213 ProgIF = 0x00
214 BAR0 = 0x00000001
215 BAR1 = 0x00000000
216 BAR2 = 0x00000000
217 BAR3 = 0x00000000
218 BAR4 = 0x00000000
219 BAR5 = 0x00000000
220 MaximumLatency = 0x34
221 MinimumGrant = 0xb0
222 InterruptLine = 0x1e
223 InterruptPin = 0x01
224 BAR0Size = '256B'
225 BAR1Size = '4kB'
226
227
228
229class Sinic(EtherDevBase):
230 type = 'Sinic'
231 cxx_class = 'Sinic::Device'
232 cxx_header = "dev/net/sinic.hh"
233
234 rx_max_copy = Param.MemorySize('1514B', "rx max copy")
235 tx_max_copy = Param.MemorySize('16kB', "tx max copy")
236 rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
237 rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold")
238 rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold")
239 tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
240 tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold")
241 virtual_count = Param.UInt32(1, "Virtualized SINIC")
242 zero_copy_size = Param.UInt32(64, "Bytes to copy if below threshold")
243 zero_copy_threshold = Param.UInt32(256,
244 "Only zero copy above this threshold")
245 zero_copy = Param.Bool(False, "Zero copy receive")
246 delay_copy = Param.Bool(False, "Delayed copy transmit")
247 virtual_addr = Param.Bool(False, "Virtual addressing")
248
249 VendorID = 0x1291
250 DeviceID = 0x1293
251 Status = 0x0290
252 SubClassCode = 0x00
253 ClassCode = 0x02
254 ProgIF = 0x00
255 BAR0 = 0x00000000
256 BAR1 = 0x00000000
257 BAR2 = 0x00000000
258 BAR3 = 0x00000000
259 BAR4 = 0x00000000
260 BAR5 = 0x00000000
261 MaximumLatency = 0x34
262 MinimumGrant = 0xb0
263 InterruptLine = 0x1e
264 InterruptPin = 0x01
265 BAR0Size = '64kB'
266
267
| 115class EtherTapStub(EtherTapBase):
116 type = 'EtherTapStub'
117 cxx_header = "dev/net/ethertap.hh"
118 port = Param.UInt16(3500, "Port helper should send packets to")
119
120class EtherDump(SimObject):
121 type = 'EtherDump'
122 cxx_header = "dev/net/etherdump.hh"
123 file = Param.String("dump file")
124 maxlen = Param.Int(96, "max portion of packet data to dump")
125
126class EtherDevice(PciDevice):
127 type = 'EtherDevice'
128 abstract = True
129 cxx_header = "dev/net/etherdevice.hh"
130 interface = MasterPort("Ethernet Interface")
131
132class IGbE(EtherDevice):
133 # Base class for two IGbE adapters listed above
134 type = 'IGbE'
135 cxx_header = "dev/net/i8254xGBe.hh"
136 hardware_address = Param.EthernetAddr(NextEthernetAddr,
137 "Ethernet Hardware Address")
138 rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
139 tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
140 rx_desc_cache_size = Param.Int(64,
141 "Number of enteries in the rx descriptor cache")
142 tx_desc_cache_size = Param.Int(64,
143 "Number of enteries in the rx descriptor cache")
144 VendorID = 0x8086
145 SubsystemID = 0x1008
146 SubsystemVendorID = 0x8086
147 Status = 0x0000
148 SubClassCode = 0x00
149 ClassCode = 0x02
150 ProgIF = 0x00
151 BAR0 = 0x00000000
152 BAR1 = 0x00000000
153 BAR2 = 0x00000000
154 BAR3 = 0x00000000
155 BAR4 = 0x00000000
156 BAR5 = 0x00000000
157 MaximumLatency = 0x00
158 MinimumGrant = 0xff
159 InterruptLine = 0x1e
160 InterruptPin = 0x01
161 BAR0Size = '128kB'
162 wb_delay = Param.Latency('10ns', "delay before desc writeback occurs")
163 fetch_delay = Param.Latency('10ns', "delay before desc fetch occurs")
164 fetch_comp_delay = Param.Latency('10ns', "delay after desc fetch occurs")
165 wb_comp_delay = Param.Latency('10ns', "delay after desc wb occurs")
166 tx_read_delay = Param.Latency('0ns', "delay after tx dma read")
167 rx_write_delay = Param.Latency('0ns', "delay after rx dma read")
168 phy_pid = Param.UInt16("Phy PID that corresponds to device ID")
169 phy_epid = Param.UInt16("Phy EPID that corresponds to device ID")
170
171class IGbE_e1000(IGbE):
172 # Older Intel 8254x based gigabit ethernet adapter
173 # Uses Intel e1000 driver
174 DeviceID = 0x1075
175 phy_pid = 0x02A8
176 phy_epid = 0x0380
177
178class IGbE_igb(IGbE):
179 # Newer Intel 8257x based gigabit ethernet adapter
180 # Uses Intel igb driver and in theory supports packet splitting and LRO
181 DeviceID = 0x10C9
182 phy_pid = 0x0141
183 phy_epid = 0x0CC0
184
185class EtherDevBase(EtherDevice):
186 type = 'EtherDevBase'
187 abstract = True
188 cxx_header = "dev/net/etherdevice.hh"
189
190 hardware_address = Param.EthernetAddr(NextEthernetAddr,
191 "Ethernet Hardware Address")
192
193 dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
194 dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
195 dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
196 dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
197
198 rx_delay = Param.Latency('1us', "Receive Delay")
199 tx_delay = Param.Latency('1us', "Transmit Delay")
200 rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo")
201 tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo")
202
203 rx_filter = Param.Bool(True, "Enable Receive Filter")
204 intr_delay = Param.Latency('10us', "Interrupt propagation delay")
205 rx_thread = Param.Bool(False, "dedicated kernel thread for transmit")
206 tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
207 rss = Param.Bool(False, "Receive Side Scaling")
208
209class NSGigE(EtherDevBase):
210 type = 'NSGigE'
211 cxx_header = "dev/net/ns_gige.hh"
212
213 dma_data_free = Param.Bool(False, "DMA of Data is free")
214 dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
215 dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
216
217 VendorID = 0x100B
218 DeviceID = 0x0022
219 Status = 0x0290
220 SubClassCode = 0x00
221 ClassCode = 0x02
222 ProgIF = 0x00
223 BAR0 = 0x00000001
224 BAR1 = 0x00000000
225 BAR2 = 0x00000000
226 BAR3 = 0x00000000
227 BAR4 = 0x00000000
228 BAR5 = 0x00000000
229 MaximumLatency = 0x34
230 MinimumGrant = 0xb0
231 InterruptLine = 0x1e
232 InterruptPin = 0x01
233 BAR0Size = '256B'
234 BAR1Size = '4kB'
235
236
237
238class Sinic(EtherDevBase):
239 type = 'Sinic'
240 cxx_class = 'Sinic::Device'
241 cxx_header = "dev/net/sinic.hh"
242
243 rx_max_copy = Param.MemorySize('1514B', "rx max copy")
244 tx_max_copy = Param.MemorySize('16kB', "tx max copy")
245 rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
246 rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold")
247 rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold")
248 tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
249 tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold")
250 virtual_count = Param.UInt32(1, "Virtualized SINIC")
251 zero_copy_size = Param.UInt32(64, "Bytes to copy if below threshold")
252 zero_copy_threshold = Param.UInt32(256,
253 "Only zero copy above this threshold")
254 zero_copy = Param.Bool(False, "Zero copy receive")
255 delay_copy = Param.Bool(False, "Delayed copy transmit")
256 virtual_addr = Param.Bool(False, "Virtual addressing")
257
258 VendorID = 0x1291
259 DeviceID = 0x1293
260 Status = 0x0290
261 SubClassCode = 0x00
262 ClassCode = 0x02
263 ProgIF = 0x00
264 BAR0 = 0x00000000
265 BAR1 = 0x00000000
266 BAR2 = 0x00000000
267 BAR3 = 0x00000000
268 BAR4 = 0x00000000
269 BAR5 = 0x00000000
270 MaximumLatency = 0x34
271 MinimumGrant = 0xb0
272 InterruptLine = 0x1e
273 InterruptPin = 0x01
274 BAR0Size = '64kB'
275
276
|