1# Copyright (c) 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Nathan Binkert
40
41from m5.SimObject import SimObject
42from m5.params import *
43from m5.proxy import *
44from PciDevice import PciDevice
45
46class EtherObject(SimObject):
47 type = 'EtherObject'
48 abstract = True
49 cxx_header = "dev/net/etherobject.hh"
50
51class EtherLink(EtherObject):
52 type = 'EtherLink'
53 cxx_header = "dev/net/etherlink.hh"
54 int0 = SlavePort("interface 0")
55 int1 = SlavePort("interface 1")
56 delay = Param.Latency('0us', "packet transmit delay")
57 delay_var = Param.Latency('0ns', "packet transmit delay variability")
58 speed = Param.NetworkBandwidth('1Gbps', "link speed")
59 dump = Param.EtherDump(NULL, "dump object")
60
| 1# Copyright (c) 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Nathan Binkert
40
41from m5.SimObject import SimObject
42from m5.params import *
43from m5.proxy import *
44from PciDevice import PciDevice
45
46class EtherObject(SimObject):
47 type = 'EtherObject'
48 abstract = True
49 cxx_header = "dev/net/etherobject.hh"
50
51class EtherLink(EtherObject):
52 type = 'EtherLink'
53 cxx_header = "dev/net/etherlink.hh"
54 int0 = SlavePort("interface 0")
55 int1 = SlavePort("interface 1")
56 delay = Param.Latency('0us', "packet transmit delay")
57 delay_var = Param.Latency('0ns', "packet transmit delay variability")
58 speed = Param.NetworkBandwidth('1Gbps', "link speed")
59 dump = Param.EtherDump(NULL, "dump object")
60
|
61class MultiEtherLink(EtherObject):
62 type = 'MultiEtherLink'
63 cxx_header = "dev/net/multi_etherlink.hh"
| 61class DistEtherLink(EtherObject):
62 type = 'DistEtherLink'
63 cxx_header = "dev/net/dist_etherlink.hh"
|
64 int0 = SlavePort("interface 0")
65 delay = Param.Latency('0us', "packet transmit delay")
66 delay_var = Param.Latency('0ns', "packet transmit delay variability")
67 speed = Param.NetworkBandwidth('1Gbps', "link speed")
68 dump = Param.EtherDump(NULL, "dump object")
| 64 int0 = SlavePort("interface 0")
65 delay = Param.Latency('0us', "packet transmit delay")
66 delay_var = Param.Latency('0ns', "packet transmit delay variability")
67 speed = Param.NetworkBandwidth('1Gbps', "link speed")
68 dump = Param.EtherDump(NULL, "dump object")
|
69 multi_rank = Param.UInt32('0', "Rank of the this gem5 process (multi run)")
70 sync_start = Param.Latency('5200000000000t', "first multi sync barrier")
71 sync_repeat = Param.Latency('10us', "multi sync barrier repeat")
| 69 dist_rank = Param.UInt32('0', "Rank of this gem5 process (dist run)")
70 dist_size = Param.UInt32('1', "Number of gem5 processes (dist run)")
71 sync_start = Param.Latency('5200000000000t', "first dist sync barrier")
72 sync_repeat = Param.Latency('10us', "dist sync barrier repeat")
|
72 server_name = Param.String('localhost', "Message server name")
73 server_port = Param.UInt32('2200', "Message server port")
| 73 server_name = Param.String('localhost', "Message server name")
74 server_port = Param.UInt32('2200', "Message server port")
|
| 75 is_switch = Param.Bool(False, "true if this a link in etherswitch")
76 num_nodes = Param.UInt32('2', "Number of simulate nodes")
|
74
75class EtherBus(EtherObject):
76 type = 'EtherBus'
77 cxx_header = "dev/net/etherbus.hh"
78 loopback = Param.Bool(True, "send packet back to the sending interface")
79 dump = Param.EtherDump(NULL, "dump object")
80 speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
81
82class EtherTap(EtherObject):
83 type = 'EtherTap'
84 cxx_header = "dev/net/ethertap.hh"
85 bufsz = Param.Int(10000, "tap buffer size")
86 dump = Param.EtherDump(NULL, "dump object")
87 port = Param.UInt16(3500, "tap port")
88
89class EtherDump(SimObject):
90 type = 'EtherDump'
91 cxx_header = "dev/net/etherdump.hh"
92 file = Param.String("dump file")
93 maxlen = Param.Int(96, "max portion of packet data to dump")
94
95class EtherDevice(PciDevice):
96 type = 'EtherDevice'
97 abstract = True
98 cxx_header = "dev/net/etherdevice.hh"
99 interface = MasterPort("Ethernet Interface")
100
101class IGbE(EtherDevice):
102 # Base class for two IGbE adapters listed above
103 type = 'IGbE'
104 cxx_header = "dev/net/i8254xGBe.hh"
105 hardware_address = Param.EthernetAddr(NextEthernetAddr,
106 "Ethernet Hardware Address")
107 rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
108 tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
109 rx_desc_cache_size = Param.Int(64,
110 "Number of enteries in the rx descriptor cache")
111 tx_desc_cache_size = Param.Int(64,
112 "Number of enteries in the rx descriptor cache")
113 VendorID = 0x8086
114 SubsystemID = 0x1008
115 SubsystemVendorID = 0x8086
116 Status = 0x0000
117 SubClassCode = 0x00
118 ClassCode = 0x02
119 ProgIF = 0x00
120 BAR0 = 0x00000000
121 BAR1 = 0x00000000
122 BAR2 = 0x00000000
123 BAR3 = 0x00000000
124 BAR4 = 0x00000000
125 BAR5 = 0x00000000
126 MaximumLatency = 0x00
127 MinimumGrant = 0xff
128 InterruptLine = 0x1e
129 InterruptPin = 0x01
130 BAR0Size = '128kB'
131 wb_delay = Param.Latency('10ns', "delay before desc writeback occurs")
132 fetch_delay = Param.Latency('10ns', "delay before desc fetch occurs")
133 fetch_comp_delay = Param.Latency('10ns', "delay after desc fetch occurs")
134 wb_comp_delay = Param.Latency('10ns', "delay after desc wb occurs")
135 tx_read_delay = Param.Latency('0ns', "delay after tx dma read")
136 rx_write_delay = Param.Latency('0ns', "delay after rx dma read")
137 phy_pid = Param.UInt16("Phy PID that corresponds to device ID")
138 phy_epid = Param.UInt16("Phy EPID that corresponds to device ID")
139
140class IGbE_e1000(IGbE):
141 # Older Intel 8254x based gigabit ethernet adapter
142 # Uses Intel e1000 driver
143 DeviceID = 0x1075
144 phy_pid = 0x02A8
145 phy_epid = 0x0380
146
147class IGbE_igb(IGbE):
148 # Newer Intel 8257x based gigabit ethernet adapter
149 # Uses Intel igb driver and in theory supports packet splitting and LRO
150 DeviceID = 0x10C9
151 phy_pid = 0x0141
152 phy_epid = 0x0CC0
153
154class EtherDevBase(EtherDevice):
155 type = 'EtherDevBase'
156 abstract = True
157 cxx_header = "dev/net/etherdevice.hh"
158
159 hardware_address = Param.EthernetAddr(NextEthernetAddr,
160 "Ethernet Hardware Address")
161
162 dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
163 dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
164 dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
165 dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
166
167 rx_delay = Param.Latency('1us', "Receive Delay")
168 tx_delay = Param.Latency('1us', "Transmit Delay")
169 rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo")
170 tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo")
171
172 rx_filter = Param.Bool(True, "Enable Receive Filter")
173 intr_delay = Param.Latency('10us', "Interrupt propagation delay")
174 rx_thread = Param.Bool(False, "dedicated kernel thread for transmit")
175 tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
176 rss = Param.Bool(False, "Receive Side Scaling")
177
178class NSGigE(EtherDevBase):
179 type = 'NSGigE'
180 cxx_header = "dev/net/ns_gige.hh"
181
182 dma_data_free = Param.Bool(False, "DMA of Data is free")
183 dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
184 dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
185
186 VendorID = 0x100B
187 DeviceID = 0x0022
188 Status = 0x0290
189 SubClassCode = 0x00
190 ClassCode = 0x02
191 ProgIF = 0x00
192 BAR0 = 0x00000001
193 BAR1 = 0x00000000
194 BAR2 = 0x00000000
195 BAR3 = 0x00000000
196 BAR4 = 0x00000000
197 BAR5 = 0x00000000
198 MaximumLatency = 0x34
199 MinimumGrant = 0xb0
200 InterruptLine = 0x1e
201 InterruptPin = 0x01
202 BAR0Size = '256B'
203 BAR1Size = '4kB'
204
205
206
207class Sinic(EtherDevBase):
208 type = 'Sinic'
209 cxx_class = 'Sinic::Device'
210 cxx_header = "dev/net/sinic.hh"
211
212 rx_max_copy = Param.MemorySize('1514B', "rx max copy")
213 tx_max_copy = Param.MemorySize('16kB', "tx max copy")
214 rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
215 rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold")
216 rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold")
217 tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
218 tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold")
219 virtual_count = Param.UInt32(1, "Virtualized SINIC")
220 zero_copy_size = Param.UInt32(64, "Bytes to copy if below threshold")
221 zero_copy_threshold = Param.UInt32(256,
222 "Only zero copy above this threshold")
223 zero_copy = Param.Bool(False, "Zero copy receive")
224 delay_copy = Param.Bool(False, "Delayed copy transmit")
225 virtual_addr = Param.Bool(False, "Virtual addressing")
226
227 VendorID = 0x1291
228 DeviceID = 0x1293
229 Status = 0x0290
230 SubClassCode = 0x00
231 ClassCode = 0x02
232 ProgIF = 0x00
233 BAR0 = 0x00000000
234 BAR1 = 0x00000000
235 BAR2 = 0x00000000
236 BAR3 = 0x00000000
237 BAR4 = 0x00000000
238 BAR5 = 0x00000000
239 MaximumLatency = 0x34
240 MinimumGrant = 0xb0
241 InterruptLine = 0x1e
242 InterruptPin = 0x01
243 BAR0Size = '64kB'
244
245
| 77
78class EtherBus(EtherObject):
79 type = 'EtherBus'
80 cxx_header = "dev/net/etherbus.hh"
81 loopback = Param.Bool(True, "send packet back to the sending interface")
82 dump = Param.EtherDump(NULL, "dump object")
83 speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
84
85class EtherTap(EtherObject):
86 type = 'EtherTap'
87 cxx_header = "dev/net/ethertap.hh"
88 bufsz = Param.Int(10000, "tap buffer size")
89 dump = Param.EtherDump(NULL, "dump object")
90 port = Param.UInt16(3500, "tap port")
91
92class EtherDump(SimObject):
93 type = 'EtherDump'
94 cxx_header = "dev/net/etherdump.hh"
95 file = Param.String("dump file")
96 maxlen = Param.Int(96, "max portion of packet data to dump")
97
98class EtherDevice(PciDevice):
99 type = 'EtherDevice'
100 abstract = True
101 cxx_header = "dev/net/etherdevice.hh"
102 interface = MasterPort("Ethernet Interface")
103
104class IGbE(EtherDevice):
105 # Base class for two IGbE adapters listed above
106 type = 'IGbE'
107 cxx_header = "dev/net/i8254xGBe.hh"
108 hardware_address = Param.EthernetAddr(NextEthernetAddr,
109 "Ethernet Hardware Address")
110 rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
111 tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
112 rx_desc_cache_size = Param.Int(64,
113 "Number of enteries in the rx descriptor cache")
114 tx_desc_cache_size = Param.Int(64,
115 "Number of enteries in the rx descriptor cache")
116 VendorID = 0x8086
117 SubsystemID = 0x1008
118 SubsystemVendorID = 0x8086
119 Status = 0x0000
120 SubClassCode = 0x00
121 ClassCode = 0x02
122 ProgIF = 0x00
123 BAR0 = 0x00000000
124 BAR1 = 0x00000000
125 BAR2 = 0x00000000
126 BAR3 = 0x00000000
127 BAR4 = 0x00000000
128 BAR5 = 0x00000000
129 MaximumLatency = 0x00
130 MinimumGrant = 0xff
131 InterruptLine = 0x1e
132 InterruptPin = 0x01
133 BAR0Size = '128kB'
134 wb_delay = Param.Latency('10ns', "delay before desc writeback occurs")
135 fetch_delay = Param.Latency('10ns', "delay before desc fetch occurs")
136 fetch_comp_delay = Param.Latency('10ns', "delay after desc fetch occurs")
137 wb_comp_delay = Param.Latency('10ns', "delay after desc wb occurs")
138 tx_read_delay = Param.Latency('0ns', "delay after tx dma read")
139 rx_write_delay = Param.Latency('0ns', "delay after rx dma read")
140 phy_pid = Param.UInt16("Phy PID that corresponds to device ID")
141 phy_epid = Param.UInt16("Phy EPID that corresponds to device ID")
142
143class IGbE_e1000(IGbE):
144 # Older Intel 8254x based gigabit ethernet adapter
145 # Uses Intel e1000 driver
146 DeviceID = 0x1075
147 phy_pid = 0x02A8
148 phy_epid = 0x0380
149
150class IGbE_igb(IGbE):
151 # Newer Intel 8257x based gigabit ethernet adapter
152 # Uses Intel igb driver and in theory supports packet splitting and LRO
153 DeviceID = 0x10C9
154 phy_pid = 0x0141
155 phy_epid = 0x0CC0
156
157class EtherDevBase(EtherDevice):
158 type = 'EtherDevBase'
159 abstract = True
160 cxx_header = "dev/net/etherdevice.hh"
161
162 hardware_address = Param.EthernetAddr(NextEthernetAddr,
163 "Ethernet Hardware Address")
164
165 dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
166 dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
167 dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
168 dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
169
170 rx_delay = Param.Latency('1us', "Receive Delay")
171 tx_delay = Param.Latency('1us', "Transmit Delay")
172 rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo")
173 tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo")
174
175 rx_filter = Param.Bool(True, "Enable Receive Filter")
176 intr_delay = Param.Latency('10us', "Interrupt propagation delay")
177 rx_thread = Param.Bool(False, "dedicated kernel thread for transmit")
178 tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
179 rss = Param.Bool(False, "Receive Side Scaling")
180
181class NSGigE(EtherDevBase):
182 type = 'NSGigE'
183 cxx_header = "dev/net/ns_gige.hh"
184
185 dma_data_free = Param.Bool(False, "DMA of Data is free")
186 dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
187 dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
188
189 VendorID = 0x100B
190 DeviceID = 0x0022
191 Status = 0x0290
192 SubClassCode = 0x00
193 ClassCode = 0x02
194 ProgIF = 0x00
195 BAR0 = 0x00000001
196 BAR1 = 0x00000000
197 BAR2 = 0x00000000
198 BAR3 = 0x00000000
199 BAR4 = 0x00000000
200 BAR5 = 0x00000000
201 MaximumLatency = 0x34
202 MinimumGrant = 0xb0
203 InterruptLine = 0x1e
204 InterruptPin = 0x01
205 BAR0Size = '256B'
206 BAR1Size = '4kB'
207
208
209
210class Sinic(EtherDevBase):
211 type = 'Sinic'
212 cxx_class = 'Sinic::Device'
213 cxx_header = "dev/net/sinic.hh"
214
215 rx_max_copy = Param.MemorySize('1514B', "rx max copy")
216 tx_max_copy = Param.MemorySize('16kB', "tx max copy")
217 rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
218 rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold")
219 rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold")
220 tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
221 tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold")
222 virtual_count = Param.UInt32(1, "Virtualized SINIC")
223 zero_copy_size = Param.UInt32(64, "Bytes to copy if below threshold")
224 zero_copy_threshold = Param.UInt32(256,
225 "Only zero copy above this threshold")
226 zero_copy = Param.Bool(False, "Zero copy receive")
227 delay_copy = Param.Bool(False, "Delayed copy transmit")
228 virtual_addr = Param.Bool(False, "Virtual addressing")
229
230 VendorID = 0x1291
231 DeviceID = 0x1293
232 Status = 0x0290
233 SubClassCode = 0x00
234 ClassCode = 0x02
235 ProgIF = 0x00
236 BAR0 = 0x00000000
237 BAR1 = 0x00000000
238 BAR2 = 0x00000000
239 BAR3 = 0x00000000
240 BAR4 = 0x00000000
241 BAR5 = 0x00000000
242 MaximumLatency = 0x34
243 MinimumGrant = 0xb0
244 InterruptLine = 0x1e
245 InterruptPin = 0x01
246 BAR0Size = '64kB'
247
248
|