malta_cchip.cc (10905:a6ca6831e775) malta_cchip.cc (11321:02e930db812d)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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202 uint64_t bitvector;
203 uint64_t olddim;
204 uint64_t olddir;
205
206 olddim = dim[number];
207 olddir = dir[number];
208 dim[number] = pkt->get<uint64_t>();
209 dir[number] = dim[number] & drir;
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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202 uint64_t bitvector;
203 uint64_t olddim;
204 uint64_t olddir;
205
206 olddim = dim[number];
207 olddir = dir[number];
208 dim[number] = pkt->get<uint64_t>();
209 dir[number] = dim[number] & drir;
210 for(int x = 0; x < Malta::Max_CPUs; x++)
210 for (int x = 0; x < Malta::Max_CPUs; x++)
211 {
212 bitvector = ULL(1) << x;
213 // Figure out which bits have changed
214 if ((dim[number] & bitvector) != (olddim & bitvector))
215 {
216 // The bit is now set and it wasn't before (set)
211 {
212 bitvector = ULL(1) << x;
213 // Figure out which bits have changed
214 if ((dim[number] & bitvector) != (olddim & bitvector))
215 {
216 // The bit is now set and it wasn't before (set)
217 if((dim[number] & bitvector) && (dir[number] & bitvector))
217 if ((dim[number] & bitvector) && (dir[number] & bitvector))
218 {
219 malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
220 DPRINTF(Malta, "dim write resulting in posting dir"
221 " interrupt to cpu %d\n", number);
222 }
223 else if ((olddir & bitvector) &&
224 !(dir[number] & bitvector))
225 {

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264 clearITI(itintr);
265 supportedWrite = true;
266 }
267
268 // ignore NXMs
269 if (pkt->get<uint64_t>() & 0x10000000)
270 supportedWrite = true;
271
218 {
219 malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
220 DPRINTF(Malta, "dim write resulting in posting dir"
221 " interrupt to cpu %d\n", number);
222 }
223 else if ((olddir & bitvector) &&
224 !(dir[number] & bitvector))
225 {

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264 clearITI(itintr);
265 supportedWrite = true;
266 }
267
268 // ignore NXMs
269 if (pkt->get<uint64_t>() & 0x10000000)
270 supportedWrite = true;
271
272 if(!supportedWrite)
272 if (!supportedWrite)
273 panic("TSDEV_CC_MISC write not implemented\n");
274
275 break;
276 case TSDEV_CC_AAR0:
277 case TSDEV_CC_AAR1:
278 case TSDEV_CC_AAR2:
279 case TSDEV_CC_AAR3:
280 panic("TSDEV_CC_AARx write not implemeted\n");
281 case TSDEV_CC_DIM0:
282 case TSDEV_CC_DIM1:
283 case TSDEV_CC_DIM2:
284 case TSDEV_CC_DIM3:
285 int number;
273 panic("TSDEV_CC_MISC write not implemented\n");
274
275 break;
276 case TSDEV_CC_AAR0:
277 case TSDEV_CC_AAR1:
278 case TSDEV_CC_AAR2:
279 case TSDEV_CC_AAR3:
280 panic("TSDEV_CC_AARx write not implemeted\n");
281 case TSDEV_CC_DIM0:
282 case TSDEV_CC_DIM1:
283 case TSDEV_CC_DIM2:
284 case TSDEV_CC_DIM3:
285 int number;
286 if(regnum == TSDEV_CC_DIM0)
286 if (regnum == TSDEV_CC_DIM0)
287 number = 0;
287 number = 0;
288 else if(regnum == TSDEV_CC_DIM1)
288 else if (regnum == TSDEV_CC_DIM1)
289 number = 1;
289 number = 1;
290 else if(regnum == TSDEV_CC_DIM2)
290 else if (regnum == TSDEV_CC_DIM2)
291 number = 2;
292 else
293 number = 3;
294
295 uint64_t bitvector;
296 uint64_t olddim;
297 uint64_t olddir;
298
299 olddim = dim[number];
300 olddir = dir[number];
301 dim[number] = pkt->get<uint64_t>();
302 dir[number] = dim[number] & drir;
291 number = 2;
292 else
293 number = 3;
294
295 uint64_t bitvector;
296 uint64_t olddim;
297 uint64_t olddir;
298
299 olddim = dim[number];
300 olddir = dir[number];
301 dim[number] = pkt->get<uint64_t>();
302 dir[number] = dim[number] & drir;
303 for(int x = 0; x < 64; x++)
303 for (int x = 0; x < 64; x++)
304 {
305 bitvector = ULL(1) << x;
306 // Figure out which bits have changed
307 if ((dim[number] & bitvector) != (olddim & bitvector))
308 {
309 // The bit is now set and it wasn't before (set)
304 {
305 bitvector = ULL(1) << x;
306 // Figure out which bits have changed
307 if ((dim[number] & bitvector) != (olddim & bitvector))
308 {
309 // The bit is now set and it wasn't before (set)
310 if((dim[number] & bitvector) && (dir[number] & bitvector))
310 if ((dim[number] & bitvector) && (dir[number] & bitvector))
311 {
312 malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
313 DPRINTF(Malta, "posting dir interrupt to cpu 0\n");
314 }
315 else if ((olddir & bitvector) &&
316 !(dir[number] & bitvector))
317 {
318 // The bit was set and now its now clear and

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471}
472
473void
474MaltaCChip::postIntr(uint32_t interrupt)
475{
476 uint64_t size = sys->threadContexts.size();
477 assert(size <= Malta::Max_CPUs);
478
311 {
312 malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
313 DPRINTF(Malta, "posting dir interrupt to cpu 0\n");
314 }
315 else if ((olddir & bitvector) &&
316 !(dir[number] & bitvector))
317 {
318 // The bit was set and now its now clear and

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471}
472
473void
474MaltaCChip::postIntr(uint32_t interrupt)
475{
476 uint64_t size = sys->threadContexts.size();
477 assert(size <= Malta::Max_CPUs);
478
479 for(int i=0; i < size; i++) {
479 for (int i=0; i < size; i++) {
480 //Note: Malta does not use index, but this was added to use the pre-existing implementation
481 malta->intrctrl->post(i, interrupt, 0);
482 DPRINTF(Malta, "posting interrupt to cpu %d,"
483 "interrupt %d\n",i, interrupt);
484 }
485
486}
487
488void
489MaltaCChip::clearIntr(uint32_t interrupt)
490{
491 uint64_t size = sys->threadContexts.size();
492 assert(size <= Malta::Max_CPUs);
493
480 //Note: Malta does not use index, but this was added to use the pre-existing implementation
481 malta->intrctrl->post(i, interrupt, 0);
482 DPRINTF(Malta, "posting interrupt to cpu %d,"
483 "interrupt %d\n",i, interrupt);
484 }
485
486}
487
488void
489MaltaCChip::clearIntr(uint32_t interrupt)
490{
491 uint64_t size = sys->threadContexts.size();
492 assert(size <= Malta::Max_CPUs);
493
494 for(int i=0; i < size; i++) {
494 for (int i=0; i < size; i++) {
495 //Note: Malta does not use index, but this was added to use the pre-existing implementation
496 malta->intrctrl->clear(i, interrupt, 0);
497 DPRINTF(Malta, "clearing interrupt to cpu %d,"
498 "interrupt %d\n",i, interrupt);
499 }
500}
501
502

--- 26 unchanged lines hidden --- 		495 //Note: Malta does not use index, but this was added to use the pre-existing implementation
496 malta->intrctrl->clear(i, interrupt, 0);
497 DPRINTF(Malta, "clearing interrupt to cpu %d,"
498 "interrupt %d\n",i, interrupt);
499 }
500}
501
502

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