1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Rick Strong
30 */
31
32/** @file
33 * Emulation of the Malta CChip CSRs
34 */
35
36#include <deque>
37#include <string>
38#include <vector>
39
40#include "base/trace.hh"
41#include "config/the_isa.hh"
42#include "cpu/intr_control.hh"
43#include "cpu/thread_context.hh"
44#include "debug/Malta.hh"
45#include "dev/mips/malta.hh"
46#include "dev/mips/malta_cchip.hh"
47#include "dev/mips/maltareg.h"
48#include "mem/packet.hh"
49#include "mem/packet_access.hh"
50#include "mem/port.hh"
51#include "params/MaltaCChip.hh"
52#include "sim/system.hh"
53
54using namespace std;
55using namespace TheISA;
56
57MaltaCChip::MaltaCChip(Params *p)
58 : BasicPioDevice(p, 0xfffffff), malta(p->malta)
59{
60 warn("MaltaCCHIP::MaltaCChip() not implemented.");
61
62 //Put back pointer in malta
63 malta->cchip = this;
64
65}
66
67Tick
68MaltaCChip::read(PacketPtr pkt)
69{
70 panic("MaltaCCHIP::read() not implemented.");
71 return pioDelay;
72 /*
73 DPRINTF(Malta, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
74
75 assert(pkt->result == Packet::Unknown);
76 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
77
78 Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
79 Addr daddr = (pkt->getAddr() - pioAddr);
80
81 switch (pkt->getSize()) {
82
83 case sizeof(uint64_t):
84 if (daddr & TSDEV_CC_BDIMS)
85 {
86 pkt->set(dim[(daddr >> 4) & 0x3F]);
87 break;
88 }
89
90 if (daddr & TSDEV_CC_BDIRS)
91 {
92 pkt->set(dir[(daddr >> 4) & 0x3F]);
93 break;
94 }
95
96 switch(regnum) {
97 case TSDEV_CC_CSR:
98 pkt->set(0x0);
99 break;
100 case TSDEV_CC_MTR:
101 panic("TSDEV_CC_MTR not implemeted\n");
102 break;
103 case TSDEV_CC_MISC:
104 pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF |
105 (pkt->req->contextId() & 0x3));
106 break;
107 case TSDEV_CC_AAR0:
108 case TSDEV_CC_AAR1:
109 case TSDEV_CC_AAR2:
110 case TSDEV_CC_AAR3:
111 pkt->set(0);
112 break;
113 case TSDEV_CC_DIM0:
114 pkt->set(dim[0]);
115 break;
116 case TSDEV_CC_DIM1:
117 pkt->set(dim[1]);
118 break;
119 case TSDEV_CC_DIM2:
120 pkt->set(dim[2]);
121 break;
122 case TSDEV_CC_DIM3:
123 pkt->set(dim[3]);
124 break;
125 case TSDEV_CC_DIR0:
126 pkt->set(dir[0]);
127 break;
128 case TSDEV_CC_DIR1:
129 pkt->set(dir[1]);
130 break;
131 case TSDEV_CC_DIR2:
132 pkt->set(dir[2]);
133 break;
134 case TSDEV_CC_DIR3:
135 pkt->set(dir[3]);
136 break;
137 case TSDEV_CC_DRIR:
138 pkt->set(drir);
139 break;
140 case TSDEV_CC_PRBEN:
141 panic("TSDEV_CC_PRBEN not implemented\n");
142 break;
143 case TSDEV_CC_IIC0:
144 case TSDEV_CC_IIC1:
145 case TSDEV_CC_IIC2:
146 case TSDEV_CC_IIC3:
147 panic("TSDEV_CC_IICx not implemented\n");
148 break;
149 case TSDEV_CC_MPR0:
150 case TSDEV_CC_MPR1:
151 case TSDEV_CC_MPR2:
152 case TSDEV_CC_MPR3:
153 panic("TSDEV_CC_MPRx not implemented\n");
154 break;
155 case TSDEV_CC_IPIR:
156 pkt->set(ipint);
157 break;
158 case TSDEV_CC_ITIR:
159 pkt->set(itint);
160 break;
161 default:
162 panic("default in cchip read reached, accessing 0x%x\n");
163 } // uint64_t
164
165 break;
166 case sizeof(uint32_t):
167 case sizeof(uint16_t):
168 case sizeof(uint8_t):
169 default:
170 panic("invalid access size(?) for malta register!\n");
171 }
172 DPRINTF(Malta, "Malta CChip: read regnum=%#x size=%d data=%lld\n",
173 regnum, pkt->getSize(), pkt->get<uint64_t>());
174
175 pkt->result = Packet::Success;
176 return pioDelay;
177 */
178}
179
180Tick
181MaltaCChip::write(PacketPtr pkt)
182{
183 panic("MaltaCCHIP::write() not implemented.");
184 return pioDelay;
185 /*
186 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
187 Addr daddr = pkt->getAddr() - pioAddr;
188 Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ;
189
190
191 assert(pkt->getSize() == sizeof(uint64_t));
192
193 DPRINTF(Malta, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>());
194
195 bool supportedWrite = false;
196
197
198 if (daddr & TSDEV_CC_BDIMS)
199 {
200 int number = (daddr >> 4) & 0x3F;
201
202 uint64_t bitvector;
203 uint64_t olddim;
204 uint64_t olddir;
205
206 olddim = dim[number];
207 olddir = dir[number];
208 dim[number] = pkt->get<uint64_t>();
209 dir[number] = dim[number] & drir;
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Rick Strong
30 */
31
32/** @file
33 * Emulation of the Malta CChip CSRs
34 */
35
36#include <deque>
37#include <string>
38#include <vector>
39
40#include "base/trace.hh"
41#include "config/the_isa.hh"
42#include "cpu/intr_control.hh"
43#include "cpu/thread_context.hh"
44#include "debug/Malta.hh"
45#include "dev/mips/malta.hh"
46#include "dev/mips/malta_cchip.hh"
47#include "dev/mips/maltareg.h"
48#include "mem/packet.hh"
49#include "mem/packet_access.hh"
50#include "mem/port.hh"
51#include "params/MaltaCChip.hh"
52#include "sim/system.hh"
53
54using namespace std;
55using namespace TheISA;
56
57MaltaCChip::MaltaCChip(Params *p)
58 : BasicPioDevice(p, 0xfffffff), malta(p->malta)
59{
60 warn("MaltaCCHIP::MaltaCChip() not implemented.");
61
62 //Put back pointer in malta
63 malta->cchip = this;
64
65}
66
67Tick
68MaltaCChip::read(PacketPtr pkt)
69{
70 panic("MaltaCCHIP::read() not implemented.");
71 return pioDelay;
72 /*
73 DPRINTF(Malta, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
74
75 assert(pkt->result == Packet::Unknown);
76 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
77
78 Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
79 Addr daddr = (pkt->getAddr() - pioAddr);
80
81 switch (pkt->getSize()) {
82
83 case sizeof(uint64_t):
84 if (daddr & TSDEV_CC_BDIMS)
85 {
86 pkt->set(dim[(daddr >> 4) & 0x3F]);
87 break;
88 }
89
90 if (daddr & TSDEV_CC_BDIRS)
91 {
92 pkt->set(dir[(daddr >> 4) & 0x3F]);
93 break;
94 }
95
96 switch(regnum) {
97 case TSDEV_CC_CSR:
98 pkt->set(0x0);
99 break;
100 case TSDEV_CC_MTR:
101 panic("TSDEV_CC_MTR not implemeted\n");
102 break;
103 case TSDEV_CC_MISC:
104 pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF |
105 (pkt->req->contextId() & 0x3));
106 break;
107 case TSDEV_CC_AAR0:
108 case TSDEV_CC_AAR1:
109 case TSDEV_CC_AAR2:
110 case TSDEV_CC_AAR3:
111 pkt->set(0);
112 break;
113 case TSDEV_CC_DIM0:
114 pkt->set(dim[0]);
115 break;
116 case TSDEV_CC_DIM1:
117 pkt->set(dim[1]);
118 break;
119 case TSDEV_CC_DIM2:
120 pkt->set(dim[2]);
121 break;
122 case TSDEV_CC_DIM3:
123 pkt->set(dim[3]);
124 break;
125 case TSDEV_CC_DIR0:
126 pkt->set(dir[0]);
127 break;
128 case TSDEV_CC_DIR1:
129 pkt->set(dir[1]);
130 break;
131 case TSDEV_CC_DIR2:
132 pkt->set(dir[2]);
133 break;
134 case TSDEV_CC_DIR3:
135 pkt->set(dir[3]);
136 break;
137 case TSDEV_CC_DRIR:
138 pkt->set(drir);
139 break;
140 case TSDEV_CC_PRBEN:
141 panic("TSDEV_CC_PRBEN not implemented\n");
142 break;
143 case TSDEV_CC_IIC0:
144 case TSDEV_CC_IIC1:
145 case TSDEV_CC_IIC2:
146 case TSDEV_CC_IIC3:
147 panic("TSDEV_CC_IICx not implemented\n");
148 break;
149 case TSDEV_CC_MPR0:
150 case TSDEV_CC_MPR1:
151 case TSDEV_CC_MPR2:
152 case TSDEV_CC_MPR3:
153 panic("TSDEV_CC_MPRx not implemented\n");
154 break;
155 case TSDEV_CC_IPIR:
156 pkt->set(ipint);
157 break;
158 case TSDEV_CC_ITIR:
159 pkt->set(itint);
160 break;
161 default:
162 panic("default in cchip read reached, accessing 0x%x\n");
163 } // uint64_t
164
165 break;
166 case sizeof(uint32_t):
167 case sizeof(uint16_t):
168 case sizeof(uint8_t):
169 default:
170 panic("invalid access size(?) for malta register!\n");
171 }
172 DPRINTF(Malta, "Malta CChip: read regnum=%#x size=%d data=%lld\n",
173 regnum, pkt->getSize(), pkt->get<uint64_t>());
174
175 pkt->result = Packet::Success;
176 return pioDelay;
177 */
178}
179
180Tick
181MaltaCChip::write(PacketPtr pkt)
182{
183 panic("MaltaCCHIP::write() not implemented.");
184 return pioDelay;
185 /*
186 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
187 Addr daddr = pkt->getAddr() - pioAddr;
188 Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ;
189
190
191 assert(pkt->getSize() == sizeof(uint64_t));
192
193 DPRINTF(Malta, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>());
194
195 bool supportedWrite = false;
196
197
198 if (daddr & TSDEV_CC_BDIMS)
199 {
200 int number = (daddr >> 4) & 0x3F;
201
202 uint64_t bitvector;
203 uint64_t olddim;
204 uint64_t olddir;
205
206 olddim = dim[number];
207 olddir = dir[number];
208 dim[number] = pkt->get<uint64_t>();
209 dir[number] = dim[number] & drir;
|
210 for(int x = 0; x < Malta::Max_CPUs; x++)
| 210 for (int x = 0; x < Malta::Max_CPUs; x++)
|
211 {
212 bitvector = ULL(1) << x;
213 // Figure out which bits have changed
214 if ((dim[number] & bitvector) != (olddim & bitvector))
215 {
216 // The bit is now set and it wasn't before (set)
| 211 {
212 bitvector = ULL(1) << x;
213 // Figure out which bits have changed
214 if ((dim[number] & bitvector) != (olddim & bitvector))
215 {
216 // The bit is now set and it wasn't before (set)
|
217 if((dim[number] & bitvector) && (dir[number] & bitvector))
| 217 if ((dim[number] & bitvector) && (dir[number] & bitvector))
|
218 {
219 malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
220 DPRINTF(Malta, "dim write resulting in posting dir"
221 " interrupt to cpu %d\n", number);
222 }
223 else if ((olddir & bitvector) &&
224 !(dir[number] & bitvector))
225 {
226 // The bit was set and now its now clear and
227 // we were interrupting on that bit before
228 malta->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
229 DPRINTF(Malta, "dim write resulting in clear"
230 " dir interrupt to cpu %d\n", number);
231
232 }
233
234
235 }
236 }
237 } else {
238 switch(regnum) {
239 case TSDEV_CC_CSR:
240 panic("TSDEV_CC_CSR write\n");
241 case TSDEV_CC_MTR:
242 panic("TSDEV_CC_MTR write not implemented\n");
243 case TSDEV_CC_MISC:
244 uint64_t ipreq;
245 ipreq = (pkt->get<uint64_t>() >> 12) & 0xF;
246 //If it is bit 12-15, this is an IPI post
247 if (ipreq) {
248 reqIPI(ipreq);
249 supportedWrite = true;
250 }
251
252 //If it is bit 8-11, this is an IPI clear
253 uint64_t ipintr;
254 ipintr = (pkt->get<uint64_t>() >> 8) & 0xF;
255 if (ipintr) {
256 clearIPI(ipintr);
257 supportedWrite = true;
258 }
259
260 //If it is the 4-7th bit, clear the RTC interrupt
261 uint64_t itintr;
262 itintr = (pkt->get<uint64_t>() >> 4) & 0xF;
263 if (itintr) {
264 clearITI(itintr);
265 supportedWrite = true;
266 }
267
268 // ignore NXMs
269 if (pkt->get<uint64_t>() & 0x10000000)
270 supportedWrite = true;
271
| 218 {
219 malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
220 DPRINTF(Malta, "dim write resulting in posting dir"
221 " interrupt to cpu %d\n", number);
222 }
223 else if ((olddir & bitvector) &&
224 !(dir[number] & bitvector))
225 {
226 // The bit was set and now its now clear and
227 // we were interrupting on that bit before
228 malta->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
229 DPRINTF(Malta, "dim write resulting in clear"
230 " dir interrupt to cpu %d\n", number);
231
232 }
233
234
235 }
236 }
237 } else {
238 switch(regnum) {
239 case TSDEV_CC_CSR:
240 panic("TSDEV_CC_CSR write\n");
241 case TSDEV_CC_MTR:
242 panic("TSDEV_CC_MTR write not implemented\n");
243 case TSDEV_CC_MISC:
244 uint64_t ipreq;
245 ipreq = (pkt->get<uint64_t>() >> 12) & 0xF;
246 //If it is bit 12-15, this is an IPI post
247 if (ipreq) {
248 reqIPI(ipreq);
249 supportedWrite = true;
250 }
251
252 //If it is bit 8-11, this is an IPI clear
253 uint64_t ipintr;
254 ipintr = (pkt->get<uint64_t>() >> 8) & 0xF;
255 if (ipintr) {
256 clearIPI(ipintr);
257 supportedWrite = true;
258 }
259
260 //If it is the 4-7th bit, clear the RTC interrupt
261 uint64_t itintr;
262 itintr = (pkt->get<uint64_t>() >> 4) & 0xF;
263 if (itintr) {
264 clearITI(itintr);
265 supportedWrite = true;
266 }
267
268 // ignore NXMs
269 if (pkt->get<uint64_t>() & 0x10000000)
270 supportedWrite = true;
271
|
272 if(!supportedWrite)
| 272 if (!supportedWrite)
|
273 panic("TSDEV_CC_MISC write not implemented\n");
274
275 break;
276 case TSDEV_CC_AAR0:
277 case TSDEV_CC_AAR1:
278 case TSDEV_CC_AAR2:
279 case TSDEV_CC_AAR3:
280 panic("TSDEV_CC_AARx write not implemeted\n");
281 case TSDEV_CC_DIM0:
282 case TSDEV_CC_DIM1:
283 case TSDEV_CC_DIM2:
284 case TSDEV_CC_DIM3:
285 int number;
| 273 panic("TSDEV_CC_MISC write not implemented\n");
274
275 break;
276 case TSDEV_CC_AAR0:
277 case TSDEV_CC_AAR1:
278 case TSDEV_CC_AAR2:
279 case TSDEV_CC_AAR3:
280 panic("TSDEV_CC_AARx write not implemeted\n");
281 case TSDEV_CC_DIM0:
282 case TSDEV_CC_DIM1:
283 case TSDEV_CC_DIM2:
284 case TSDEV_CC_DIM3:
285 int number;
|
286 if(regnum == TSDEV_CC_DIM0)
| 286 if (regnum == TSDEV_CC_DIM0)
|
287 number = 0;
| 287 number = 0;
|
288 else if(regnum == TSDEV_CC_DIM1)
| 288 else if (regnum == TSDEV_CC_DIM1)
|
289 number = 1;
| 289 number = 1;
|
290 else if(regnum == TSDEV_CC_DIM2)
| 290 else if (regnum == TSDEV_CC_DIM2)
|
291 number = 2;
292 else
293 number = 3;
294
295 uint64_t bitvector;
296 uint64_t olddim;
297 uint64_t olddir;
298
299 olddim = dim[number];
300 olddir = dir[number];
301 dim[number] = pkt->get<uint64_t>();
302 dir[number] = dim[number] & drir;
| 291 number = 2;
292 else
293 number = 3;
294
295 uint64_t bitvector;
296 uint64_t olddim;
297 uint64_t olddir;
298
299 olddim = dim[number];
300 olddir = dir[number];
301 dim[number] = pkt->get<uint64_t>();
302 dir[number] = dim[number] & drir;
|
303 for(int x = 0; x < 64; x++)
| 303 for (int x = 0; x < 64; x++)
|
304 {
305 bitvector = ULL(1) << x;
306 // Figure out which bits have changed
307 if ((dim[number] & bitvector) != (olddim & bitvector))
308 {
309 // The bit is now set and it wasn't before (set)
| 304 {
305 bitvector = ULL(1) << x;
306 // Figure out which bits have changed
307 if ((dim[number] & bitvector) != (olddim & bitvector))
308 {
309 // The bit is now set and it wasn't before (set)
|
310 if((dim[number] & bitvector) && (dir[number] & bitvector))
| 310 if ((dim[number] & bitvector) && (dir[number] & bitvector))
|
311 {
312 malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
313 DPRINTF(Malta, "posting dir interrupt to cpu 0\n");
314 }
315 else if ((olddir & bitvector) &&
316 !(dir[number] & bitvector))
317 {
318 // The bit was set and now its now clear and
319 // we were interrupting on that bit before
320 malta->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
321 DPRINTF(Malta, "dim write resulting in clear"
322 " dir interrupt to cpu %d\n",
323 x);
324
325 }
326
327
328 }
329 }
330 break;
331 case TSDEV_CC_DIR0:
332 case TSDEV_CC_DIR1:
333 case TSDEV_CC_DIR2:
334 case TSDEV_CC_DIR3:
335 panic("TSDEV_CC_DIR write not implemented\n");
336 case TSDEV_CC_DRIR:
337 panic("TSDEV_CC_DRIR write not implemented\n");
338 case TSDEV_CC_PRBEN:
339 panic("TSDEV_CC_PRBEN write not implemented\n");
340 case TSDEV_CC_IIC0:
341 case TSDEV_CC_IIC1:
342 case TSDEV_CC_IIC2:
343 case TSDEV_CC_IIC3:
344 panic("TSDEV_CC_IICx write not implemented\n");
345 case TSDEV_CC_MPR0:
346 case TSDEV_CC_MPR1:
347 case TSDEV_CC_MPR2:
348 case TSDEV_CC_MPR3:
349 panic("TSDEV_CC_MPRx write not implemented\n");
350 case TSDEV_CC_IPIR:
351 clearIPI(pkt->get<uint64_t>());
352 break;
353 case TSDEV_CC_ITIR:
354 clearITI(pkt->get<uint64_t>());
355 break;
356 case TSDEV_CC_IPIQ:
357 reqIPI(pkt->get<uint64_t>());
358 break;
359 default:
360 panic("default in cchip read reached, accessing 0x%x\n");
361 } // swtich(regnum)
362 } // not BIG_TSUNAMI write
363 pkt->result = Packet::Success;
364 return pioDelay;
365 */
366}
367
368void
369MaltaCChip::clearIPI(uint64_t ipintr)
370{
371 panic("MaltaCCHIP::clear() not implemented.");
372 /*
373 int numcpus = malta->intrctrl->cpu->system->threadContexts.size();
374 assert(numcpus <= Malta::Max_CPUs);
375
376 if (ipintr) {
377 for (int cpunum=0; cpunum < numcpus; cpunum++) {
378 // Check each cpu bit
379 uint64_t cpumask = ULL(1) << cpunum;
380 if (ipintr & cpumask) {
381 // Check if there is a pending ipi
382 if (ipint & cpumask) {
383 ipint &= ~cpumask;
384 malta->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
385 DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
386 }
387 else
388 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
389 }
390 }
391 }
392 else
393 panic("Big IPI Clear, but not processors indicated\n");
394 */
395}
396
397void
398MaltaCChip::clearITI(uint64_t itintr)
399{
400 panic("MaltaCCHIP::clearITI() not implemented.");
401 /*
402 int numcpus = malta->intrctrl->cpu->system->threadContexts.size();
403 assert(numcpus <= Malta::Max_CPUs);
404
405 if (itintr) {
406 for (int i=0; i < numcpus; i++) {
407 uint64_t cpumask = ULL(1) << i;
408 if (itintr & cpumask & itint) {
409 malta->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
410 itint &= ~cpumask;
411 DPRINTF(Malta, "clearing rtc interrupt to cpu=%d\n", i);
412 }
413 }
414 }
415 else
416 panic("Big ITI Clear, but not processors indicated\n");
417 */
418}
419
420void
421MaltaCChip::reqIPI(uint64_t ipreq)
422{
423 panic("MaltaCCHIP::reqIPI() not implemented.");
424
425 /*
426 int numcpus = malta->intrctrl->cpu->system->threadContexts.size();
427 assert(numcpus <= Malta::Max_CPUs);
428
429 if (ipreq) {
430 for (int cpunum=0; cpunum < numcpus; cpunum++) {
431 // Check each cpu bit
432 uint64_t cpumask = ULL(1) << cpunum;
433 if (ipreq & cpumask) {
434 // Check if there is already an ipi (bits 8:11)
435 if (!(ipint & cpumask)) {
436 ipint |= cpumask;
437 malta->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
438 DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
439 }
440 else
441 warn("post IPI for CPU=%d, but IPI already\n", cpunum);
442 }
443 }
444 }
445 else
446 panic("Big IPI Request, but not processors indicated\n");
447 */
448
449}
450
451
452void
453MaltaCChip::postRTC()
454{
455 panic("MaltaCCHIP::postRTC() not implemented.");
456
457 /*
458 int size = malta->intrctrl->cpu->system->threadContexts.size();
459 assert(size <= Malta::Max_CPUs);
460
461 for (int i = 0; i < size; i++) {
462 uint64_t cpumask = ULL(1) << i;
463 if (!(cpumask & itint)) {
464 itint |= cpumask;
465 malta->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
466 DPRINTF(Malta, "Posting RTC interrupt to cpu=%d", i);
467 }
468 }
469 */
470
471}
472
473void
474MaltaCChip::postIntr(uint32_t interrupt)
475{
476 uint64_t size = sys->threadContexts.size();
477 assert(size <= Malta::Max_CPUs);
478
| 311 {
312 malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
313 DPRINTF(Malta, "posting dir interrupt to cpu 0\n");
314 }
315 else if ((olddir & bitvector) &&
316 !(dir[number] & bitvector))
317 {
318 // The bit was set and now its now clear and
319 // we were interrupting on that bit before
320 malta->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
321 DPRINTF(Malta, "dim write resulting in clear"
322 " dir interrupt to cpu %d\n",
323 x);
324
325 }
326
327
328 }
329 }
330 break;
331 case TSDEV_CC_DIR0:
332 case TSDEV_CC_DIR1:
333 case TSDEV_CC_DIR2:
334 case TSDEV_CC_DIR3:
335 panic("TSDEV_CC_DIR write not implemented\n");
336 case TSDEV_CC_DRIR:
337 panic("TSDEV_CC_DRIR write not implemented\n");
338 case TSDEV_CC_PRBEN:
339 panic("TSDEV_CC_PRBEN write not implemented\n");
340 case TSDEV_CC_IIC0:
341 case TSDEV_CC_IIC1:
342 case TSDEV_CC_IIC2:
343 case TSDEV_CC_IIC3:
344 panic("TSDEV_CC_IICx write not implemented\n");
345 case TSDEV_CC_MPR0:
346 case TSDEV_CC_MPR1:
347 case TSDEV_CC_MPR2:
348 case TSDEV_CC_MPR3:
349 panic("TSDEV_CC_MPRx write not implemented\n");
350 case TSDEV_CC_IPIR:
351 clearIPI(pkt->get<uint64_t>());
352 break;
353 case TSDEV_CC_ITIR:
354 clearITI(pkt->get<uint64_t>());
355 break;
356 case TSDEV_CC_IPIQ:
357 reqIPI(pkt->get<uint64_t>());
358 break;
359 default:
360 panic("default in cchip read reached, accessing 0x%x\n");
361 } // swtich(regnum)
362 } // not BIG_TSUNAMI write
363 pkt->result = Packet::Success;
364 return pioDelay;
365 */
366}
367
368void
369MaltaCChip::clearIPI(uint64_t ipintr)
370{
371 panic("MaltaCCHIP::clear() not implemented.");
372 /*
373 int numcpus = malta->intrctrl->cpu->system->threadContexts.size();
374 assert(numcpus <= Malta::Max_CPUs);
375
376 if (ipintr) {
377 for (int cpunum=0; cpunum < numcpus; cpunum++) {
378 // Check each cpu bit
379 uint64_t cpumask = ULL(1) << cpunum;
380 if (ipintr & cpumask) {
381 // Check if there is a pending ipi
382 if (ipint & cpumask) {
383 ipint &= ~cpumask;
384 malta->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
385 DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
386 }
387 else
388 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
389 }
390 }
391 }
392 else
393 panic("Big IPI Clear, but not processors indicated\n");
394 */
395}
396
397void
398MaltaCChip::clearITI(uint64_t itintr)
399{
400 panic("MaltaCCHIP::clearITI() not implemented.");
401 /*
402 int numcpus = malta->intrctrl->cpu->system->threadContexts.size();
403 assert(numcpus <= Malta::Max_CPUs);
404
405 if (itintr) {
406 for (int i=0; i < numcpus; i++) {
407 uint64_t cpumask = ULL(1) << i;
408 if (itintr & cpumask & itint) {
409 malta->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
410 itint &= ~cpumask;
411 DPRINTF(Malta, "clearing rtc interrupt to cpu=%d\n", i);
412 }
413 }
414 }
415 else
416 panic("Big ITI Clear, but not processors indicated\n");
417 */
418}
419
420void
421MaltaCChip::reqIPI(uint64_t ipreq)
422{
423 panic("MaltaCCHIP::reqIPI() not implemented.");
424
425 /*
426 int numcpus = malta->intrctrl->cpu->system->threadContexts.size();
427 assert(numcpus <= Malta::Max_CPUs);
428
429 if (ipreq) {
430 for (int cpunum=0; cpunum < numcpus; cpunum++) {
431 // Check each cpu bit
432 uint64_t cpumask = ULL(1) << cpunum;
433 if (ipreq & cpumask) {
434 // Check if there is already an ipi (bits 8:11)
435 if (!(ipint & cpumask)) {
436 ipint |= cpumask;
437 malta->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
438 DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
439 }
440 else
441 warn("post IPI for CPU=%d, but IPI already\n", cpunum);
442 }
443 }
444 }
445 else
446 panic("Big IPI Request, but not processors indicated\n");
447 */
448
449}
450
451
452void
453MaltaCChip::postRTC()
454{
455 panic("MaltaCCHIP::postRTC() not implemented.");
456
457 /*
458 int size = malta->intrctrl->cpu->system->threadContexts.size();
459 assert(size <= Malta::Max_CPUs);
460
461 for (int i = 0; i < size; i++) {
462 uint64_t cpumask = ULL(1) << i;
463 if (!(cpumask & itint)) {
464 itint |= cpumask;
465 malta->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
466 DPRINTF(Malta, "Posting RTC interrupt to cpu=%d", i);
467 }
468 }
469 */
470
471}
472
473void
474MaltaCChip::postIntr(uint32_t interrupt)
475{
476 uint64_t size = sys->threadContexts.size();
477 assert(size <= Malta::Max_CPUs);
478
|
479 for(int i=0; i < size; i++) {
| 479 for (int i=0; i < size; i++) {
|
480 //Note: Malta does not use index, but this was added to use the pre-existing implementation
481 malta->intrctrl->post(i, interrupt, 0);
482 DPRINTF(Malta, "posting interrupt to cpu %d,"
483 "interrupt %d\n",i, interrupt);
484 }
485
486}
487
488void
489MaltaCChip::clearIntr(uint32_t interrupt)
490{
491 uint64_t size = sys->threadContexts.size();
492 assert(size <= Malta::Max_CPUs);
493
| 480 //Note: Malta does not use index, but this was added to use the pre-existing implementation
481 malta->intrctrl->post(i, interrupt, 0);
482 DPRINTF(Malta, "posting interrupt to cpu %d,"
483 "interrupt %d\n",i, interrupt);
484 }
485
486}
487
488void
489MaltaCChip::clearIntr(uint32_t interrupt)
490{
491 uint64_t size = sys->threadContexts.size();
492 assert(size <= Malta::Max_CPUs);
493
|
494 for(int i=0; i < size; i++) {
| 494 for (int i=0; i < size; i++) {
|
495 //Note: Malta does not use index, but this was added to use the pre-existing implementation
496 malta->intrctrl->clear(i, interrupt, 0);
497 DPRINTF(Malta, "clearing interrupt to cpu %d,"
498 "interrupt %d\n",i, interrupt);
499 }
500}
501
502
503void
504MaltaCChip::serialize(CheckpointOut &cp) const
505{
506 // SERIALIZE_ARRAY(dim, Malta::Max_CPUs);
507 //SERIALIZE_ARRAY(dir, Malta::Max_CPUs);
508 //SERIALIZE_SCALAR(ipint);
509 //SERIALIZE_SCALAR(itint);
510 //SERIALIZE_SCALAR(drir);
511}
512
513void
514MaltaCChip::unserialize(CheckpointIn &cp)
515{
516 //UNSERIALIZE_ARRAY(dim, Malta::Max_CPUs);
517 //UNSERIALIZE_ARRAY(dir, Malta::Max_CPUs);
518 //UNSERIALIZE_SCALAR(ipint);
519 //UNSERIALIZE_SCALAR(itint);
520 //UNSERIALIZE_SCALAR(drir);
521}
522
523MaltaCChip *
524MaltaCChipParams::create()
525{
526 return new MaltaCChip(this);
527}
528
| 495 //Note: Malta does not use index, but this was added to use the pre-existing implementation
496 malta->intrctrl->clear(i, interrupt, 0);
497 DPRINTF(Malta, "clearing interrupt to cpu %d,"
498 "interrupt %d\n",i, interrupt);
499 }
500}
501
502
503void
504MaltaCChip::serialize(CheckpointOut &cp) const
505{
506 // SERIALIZE_ARRAY(dim, Malta::Max_CPUs);
507 //SERIALIZE_ARRAY(dir, Malta::Max_CPUs);
508 //SERIALIZE_SCALAR(ipint);
509 //SERIALIZE_SCALAR(itint);
510 //SERIALIZE_SCALAR(drir);
511}
512
513void
514MaltaCChip::unserialize(CheckpointIn &cp)
515{
516 //UNSERIALIZE_ARRAY(dim, Malta::Max_CPUs);
517 //UNSERIALIZE_ARRAY(dir, Malta::Max_CPUs);
518 //UNSERIALIZE_SCALAR(ipint);
519 //UNSERIALIZE_SCALAR(itint);
520 //UNSERIALIZE_SCALAR(drir);
521}
522
523MaltaCChip *
524MaltaCChipParams::create()
525{
526 return new MaltaCChip(this);
527}
528
|