1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Rick Strong
30 */
31
32/**
33 * @file
34 * Declaration of top level class for the Malta chipset. This class just
35 * retains pointers to all its children so the children can communicate.
36 */
37
38#ifndef __DEV_MALTA_HH__
39#define __DEV_MALTA_HH__
40
41#include "dev/platform.hh"
42#include "params/Malta.hh"
43
44class IdeController;
45class MaltaCChip;
46class MaltaPChip;
47class MaltaIO;
48class System;
49
50/**
51 * Top level class for Malta Chipset emulation.
52 * This structure just contains pointers to all the
53 * children so the children can commnicate to do the
54 * read work
55 */
56
57class Malta : public Platform
58{
59 public:
60 /** Max number of CPUs in a Malta */
61 static const int Max_CPUs = 64;
62
63 /** Pointer to the system */
64 System *system;
65
66 /** Pointer to the MaltaIO device which has the RTC */
67 MaltaIO *io;
68
69 /** Pointer to the Malta CChip.
70 * The chip contains some configuration information and
71 * all the interrupt mask and status registers
72 */
73 MaltaCChip *cchip;
74
75 /** Pointer to the Malta PChip.
76 * The pchip is the interface to the PCI bus, in our case
77 * it does not have to do much.
78 */
79 MaltaPChip *pchip;
80
81 int intr_sum_type[Malta::Max_CPUs];
82 int ipi_pending[Malta::Max_CPUs];
83
84 public:
85 /**
86 * Constructor for the Malta Class.
87 * @param name name of the object
88 * @param s system the object belongs to
89 * @param intctrl pointer to the interrupt controller
90 */
91 typedef MaltaParams Params;
92 Malta(const Params *p);
93
94 /**
95 * Cause the cpu to post a serial interrupt to the CPU.
96 */
97 virtual void postConsoleInt();
98
99 /**
100 * Clear a posted CPU interrupt (id=55)
101 */
102 virtual void clearConsoleInt();
103
104 /**
105 * Cause the chipset to post a cpi interrupt to the CPU.
106 */
107 virtual void postPciInt(int line);
108
109 /**
110 * Clear a posted PCI->CPU interrupt
111 */
112 virtual void clearPciInt(int line);
113
114
115 virtual Addr pciToDma(Addr pciAddr) const;
116
117 Addr
118 calcPciConfigAddr(int bus, int dev, int func)
119 {
120 panic("Need implementation\n");
121 M5_DUMMY_RETURN
122 }
123
124 Addr
125 calcPciIOAddr(Addr addr)
126 {
127 panic("Need implementation\n");
128 M5_DUMMY_RETURN
129 }
130
131 Addr
132 calcPciMemAddr(Addr addr)
133 {
134 panic("Need implementation\n");
135 M5_DUMMY_RETURN
136 }
137
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Rick Strong
30 */
31
32/**
33 * @file
34 * Declaration of top level class for the Malta chipset. This class just
35 * retains pointers to all its children so the children can communicate.
36 */
37
38#ifndef __DEV_MALTA_HH__
39#define __DEV_MALTA_HH__
40
41#include "dev/platform.hh"
42#include "params/Malta.hh"
43
44class IdeController;
45class MaltaCChip;
46class MaltaPChip;
47class MaltaIO;
48class System;
49
50/**
51 * Top level class for Malta Chipset emulation.
52 * This structure just contains pointers to all the
53 * children so the children can commnicate to do the
54 * read work
55 */
56
57class Malta : public Platform
58{
59 public:
60 /** Max number of CPUs in a Malta */
61 static const int Max_CPUs = 64;
62
63 /** Pointer to the system */
64 System *system;
65
66 /** Pointer to the MaltaIO device which has the RTC */
67 MaltaIO *io;
68
69 /** Pointer to the Malta CChip.
70 * The chip contains some configuration information and
71 * all the interrupt mask and status registers
72 */
73 MaltaCChip *cchip;
74
75 /** Pointer to the Malta PChip.
76 * The pchip is the interface to the PCI bus, in our case
77 * it does not have to do much.
78 */
79 MaltaPChip *pchip;
80
81 int intr_sum_type[Malta::Max_CPUs];
82 int ipi_pending[Malta::Max_CPUs];
83
84 public:
85 /**
86 * Constructor for the Malta Class.
87 * @param name name of the object
88 * @param s system the object belongs to
89 * @param intctrl pointer to the interrupt controller
90 */
91 typedef MaltaParams Params;
92 Malta(const Params *p);
93
94 /**
95 * Cause the cpu to post a serial interrupt to the CPU.
96 */
97 virtual void postConsoleInt();
98
99 /**
100 * Clear a posted CPU interrupt (id=55)
101 */
102 virtual void clearConsoleInt();
103
104 /**
105 * Cause the chipset to post a cpi interrupt to the CPU.
106 */
107 virtual void postPciInt(int line);
108
109 /**
110 * Clear a posted PCI->CPU interrupt
111 */
112 virtual void clearPciInt(int line);
113
114
115 virtual Addr pciToDma(Addr pciAddr) const;
116
117 Addr
118 calcPciConfigAddr(int bus, int dev, int func)
119 {
120 panic("Need implementation\n");
121 M5_DUMMY_RETURN
122 }
123
124 Addr
125 calcPciIOAddr(Addr addr)
126 {
127 panic("Need implementation\n");
128 M5_DUMMY_RETURN
129 }
130
131 Addr
132 calcPciMemAddr(Addr addr)
133 {
134 panic("Need implementation\n");
135 M5_DUMMY_RETURN
136 }
137
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