Malta.py (7709:fc12f4d657f0) | Malta.py (8847:ef8630054b5e) |
---|---|
1# Copyright (c) 2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 49 unchanged lines hidden (view full) --- 58 cchip = MaltaCChip(pio_addr=0x801a0000000) 59 io = MaltaIO(pio_addr=0x801fc000000) 60 uart = Uart8250(pio_addr=0xBFD003F8) 61 62 # Attach I/O devices to specified bus object. Can't do this 63 # earlier, since the bus object itself is typically defined at the 64 # System level. 65 def attachIO(self, bus): | 1# Copyright (c) 2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 49 unchanged lines hidden (view full) --- 58 cchip = MaltaCChip(pio_addr=0x801a0000000) 59 io = MaltaIO(pio_addr=0x801fc000000) 60 uart = Uart8250(pio_addr=0xBFD003F8) 61 62 # Attach I/O devices to specified bus object. Can't do this 63 # earlier, since the bus object itself is typically defined at the 64 # System level. 65 def attachIO(self, bus): |
66 self.cchip.pio = bus.port 67 self.io.pio = bus.port 68 self.uart.pio = bus.port | 66 self.cchip.pio = bus.master 67 self.io.pio = bus.master 68 self.uart.pio = bus.master |