Malta.py (6379:75d4aaf7dd54) | Malta.py (7709:fc12f4d657f0) |
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1# Copyright (c) 2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 17 unchanged lines hidden (view full) --- 26# 27# Authors: Korey Sewell 28 29from m5.params import * 30from m5.proxy import * 31 32from BadDevice import BadDevice 33from Device import BasicPioDevice | 1# Copyright (c) 2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 17 unchanged lines hidden (view full) --- 26# 27# Authors: Korey Sewell 28 29from m5.params import * 30from m5.proxy import * 31 32from BadDevice import BadDevice 33from Device import BasicPioDevice |
34from MipsBackdoor import MipsBackdoor | |
35from Pci import PciConfigAll 36from Platform import Platform 37from Uart import Uart8250 38 39class MaltaCChip(BasicPioDevice): 40 type = 'MaltaCChip' 41 malta = Param.Malta(Parent.any, "Malta") 42 --- 11 unchanged lines hidden (view full) --- 54 malta = Param.Malta(Parent.any, "Malta") 55 56class Malta(Platform): 57 type = 'Malta' 58 system = Param.System(Parent.any, "system") 59 cchip = MaltaCChip(pio_addr=0x801a0000000) 60 io = MaltaIO(pio_addr=0x801fc000000) 61 uart = Uart8250(pio_addr=0xBFD003F8) | 34from Pci import PciConfigAll 35from Platform import Platform 36from Uart import Uart8250 37 38class MaltaCChip(BasicPioDevice): 39 type = 'MaltaCChip' 40 malta = Param.Malta(Parent.any, "Malta") 41 --- 11 unchanged lines hidden (view full) --- 53 malta = Param.Malta(Parent.any, "Malta") 54 55class Malta(Platform): 56 type = 'Malta' 57 system = Param.System(Parent.any, "system") 58 cchip = MaltaCChip(pio_addr=0x801a0000000) 59 io = MaltaIO(pio_addr=0x801fc000000) 60 uart = Uart8250(pio_addr=0xBFD003F8) |
62 backdoor = MipsBackdoor(pio_addr=0xBFD00F00, disk=Parent.simple_disk) | |
63 64 # Attach I/O devices to specified bus object. Can't do this 65 # earlier, since the bus object itself is typically defined at the 66 # System level. 67 def attachIO(self, bus): 68 self.cchip.pio = bus.port 69 self.io.pio = bus.port 70 self.uart.pio = bus.port | 61 62 # Attach I/O devices to specified bus object. Can't do this 63 # earlier, since the bus object itself is typically defined at the 64 # System level. 65 def attachIO(self, bus): 66 self.cchip.pio = bus.port 67 self.io.pio = bus.port 68 self.uart.pio = bus.port |
71 self.backdoor.pio = bus.port | |