Malta.py (5222:bb733a878f85) Malta.py (5481:5afd4f01c824)
1# Copyright (c) 2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Korey Sewell
28
29from m5.params import *
30from m5.proxy import *
1# Copyright (c) 2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 14 unchanged lines hidden (view full) ---

23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Korey Sewell
28
29from m5.params import *
30from m5.proxy import *
31
32from BadDevice import BadDevice
31from Device import BasicPioDevice
33from Device import BasicPioDevice
34from MipsBackdoor import MipsBackdoor
35from Pci import PciConfigAll
32from Platform import Platform
36from Platform import Platform
33from MipsConsole import MipsConsole
34from Uart import Uart8250
37from Uart import Uart8250
35from Pci import PciConfigAll
36from BadDevice import BadDevice
37
38class MaltaCChip(BasicPioDevice):
39 type = 'MaltaCChip'
40 malta = Param.Malta(Parent.any, "Malta")
41
42class MaltaIO(BasicPioDevice):
43 type = 'MaltaIO'
44 time = Param.UInt64(1136073600,

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51 malta = Param.Malta(Parent.any, "Malta")
52
53class Malta(Platform):
54 type = 'Malta'
55 system = Param.System(Parent.any, "system")
56 cchip = MaltaCChip(pio_addr=0x801a0000000)
57 io = MaltaIO(pio_addr=0x801fc000000)
58 uart = Uart8250(pio_addr=0xBFD003F8)
38
39class MaltaCChip(BasicPioDevice):
40 type = 'MaltaCChip'
41 malta = Param.Malta(Parent.any, "Malta")
42
43class MaltaIO(BasicPioDevice):
44 type = 'MaltaIO'
45 time = Param.UInt64(1136073600,

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52 malta = Param.Malta(Parent.any, "Malta")
53
54class Malta(Platform):
55 type = 'Malta'
56 system = Param.System(Parent.any, "system")
57 cchip = MaltaCChip(pio_addr=0x801a0000000)
58 io = MaltaIO(pio_addr=0x801fc000000)
59 uart = Uart8250(pio_addr=0xBFD003F8)
59 console = MipsConsole(pio_addr=0xBFD00F00, disk=Parent.simple_disk)
60 backdoor = MipsBackdoor(pio_addr=0xBFD00F00, disk=Parent.simple_disk)
60
61 # Attach I/O devices to specified bus object. Can't do this
62 # earlier, since the bus object itself is typically defined at the
63 # System level.
64 def attachIO(self, bus):
65 self.cchip.pio = bus.port
66 self.io.pio = bus.port
67 self.uart.pio = bus.port
61
62 # Attach I/O devices to specified bus object. Can't do this
63 # earlier, since the bus object itself is typically defined at the
64 # System level.
65 def attachIO(self, bus):
66 self.cchip.pio = bus.port
67 self.io.pio = bus.port
68 self.uart.pio = bus.port
68 self.console.pio = bus.port
69 self.backdoor.pio = bus.port