1# Copyright (c) 2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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32from BadDevice import BadDevice
33from Device import BasicPioDevice
34from Pci import PciConfigAll
35from Platform import Platform
36from Uart import Uart8250
37
38class MaltaCChip(BasicPioDevice):
39 type = 'MaltaCChip'
40 malta = Param.Malta(Parent.any, "Malta")
41
42class MaltaIO(BasicPioDevice):
43 type = 'MaltaIO'
44 time = Param.Time('01/01/2009',
45 "System time to use (0 for actual time, default is 1/1/06)")
46 year_is_bcd = Param.Bool(False,
47 "The RTC should interpret the year as a BCD value")
48 malta = Param.Malta(Parent.any, "Malta")
49 frequency = Param.Frequency('1024Hz', "frequency of interrupts")
50
51class MaltaPChip(BasicPioDevice):
52 type = 'MaltaPChip'
53 malta = Param.Malta(Parent.any, "Malta")
54
55class Malta(Platform):
56 type = 'Malta'
57 system = Param.System(Parent.any, "system")
58 cchip = MaltaCChip(pio_addr=0x801a0000000)
59 io = MaltaIO(pio_addr=0x801fc000000)
60 uart = Uart8250(pio_addr=0xBFD003F8)
61
62 # Attach I/O devices to specified bus object. Can't do this
63 # earlier, since the bus object itself is typically defined at the
64 # System level.
65 def attachIO(self, bus):
66 self.cchip.pio = bus.master
67 self.io.pio = bus.master
68 self.uart.pio = bus.master