mc146818.cc (9730:f3b53a5a559e) mc146818.cc (9731:16f9d1fd37da)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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139 } else {
140 switch (addr) {
141 case RTC_STAT_REGA: {
142 RtcRegA old_rega(stat_regA);
143 stat_regA = data;
144 // The "update in progress" bit is read only.
145 stat_regA.uip = old_rega;
146
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 130 unchanged lines hidden (view full) ---

139 } else {
140 switch (addr) {
141 case RTC_STAT_REGA: {
142 RtcRegA old_rega(stat_regA);
143 stat_regA = data;
144 // The "update in progress" bit is read only.
145 stat_regA.uip = old_rega;
146
147 if (stat_regA.dv != RTCA_DV_32768HZ) {
147 if (!rega_dv_disabled(stat_regA) &&
148 stat_regA.dv != RTCA_DV_32768HZ) {
148 inform("RTC: Unimplemented divider configuration: %i\n",
149 stat_regA.dv);
150 panic_unsupported = true;
151 }
152
153 if (stat_regA.rs != RTCA_RS_1024HZ) {
154 inform("RTC: Unimplemented interrupt rate: %i\n",
155 stat_regA.rs);
156 panic_unsupported = true;
157 }
149 inform("RTC: Unimplemented divider configuration: %i\n",
150 stat_regA.dv);
151 panic_unsupported = true;
152 }
153
154 if (stat_regA.rs != RTCA_RS_1024HZ) {
155 inform("RTC: Unimplemented interrupt rate: %i\n",
156 stat_regA.rs);
157 panic_unsupported = true;
158 }
159
160 if (rega_dv_disabled(stat_regA)) {
161 // The divider is disabled, make sure that we don't
162 // schedule any ticks.
163 if (tickEvent.scheduled())
164 deschedule(tickEvent);
165 } else if (rega_dv_disabled(old_rega)) {
166 // If the divider chain goes from reset to active, we
167 // need to schedule a tick after precisely 0.5s.
168 assert(!tickEvent.scheduled());
169 schedule(tickEvent, curTick() + SimClock::Int::s / 2);
170 }
158 } break;
159 case RTC_STAT_REGB:
160 stat_regB = data;
171 } break;
172 case RTC_STAT_REGB:
173 stat_regB = data;
161 if (stat_regB.set) {
162 inform("RTC: Updating stopping not implemented.\n");
163 panic_unsupported = true;
164 }
165
166 if (stat_regB.aie || stat_regB.uie) {
167 inform("RTC: Unimplemented interrupt configuration: %s %s\n",
168 stat_regB.aie ? "alarm" : "",
169 stat_regB.uie ? "update" : "");
170 panic_unsupported = true;
171 }
172
173 if (stat_regB.dm) {

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228 panic("Shouldn't be here");
229 }
230 }
231}
232
233void
234MC146818::tickClock()
235{
174 if (stat_regB.aie || stat_regB.uie) {
175 inform("RTC: Unimplemented interrupt configuration: %s %s\n",
176 stat_regB.aie ? "alarm" : "",
177 stat_regB.uie ? "update" : "");
178 panic_unsupported = true;
179 }
180
181 if (stat_regB.dm) {

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236 panic("Shouldn't be here");
237 }
238 }
239}
240
241void
242MC146818::tickClock()
243{
244 assert(!rega_dv_disabled(stat_regA));
245
236 if (stat_regB.set)
237 return;
238 time_t calTime = mkutctime(&curTime);
239 calTime++;
240 setTime(*gmtime(&calTime));
241}
242
243void

--- 84 unchanged lines hidden --- 		246 if (stat_regB.set)
247 return;
248 time_t calTime = mkutctime(&curTime);
249 calTime++;
250 setTime(*gmtime(&calTime));
251}
252
253void

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