1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 * Andrew Schultz 30 * Miguel Serrano 31 */ 32 33#include <sys/time.h> 34#include <time.h> 35 36#include <string> 37 38#include "base/bitfield.hh" 39#include "base/time.hh" 40#include "base/trace.hh" 41#include "dev/mc146818.hh" 42#include "dev/rtcreg.h"
| 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 * Andrew Schultz 30 * Miguel Serrano 31 */ 32 33#include <sys/time.h> 34#include <time.h> 35 36#include <string> 37 38#include "base/bitfield.hh" 39#include "base/time.hh" 40#include "base/trace.hh" 41#include "dev/mc146818.hh" 42#include "dev/rtcreg.h"
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| 43#include "sim/sim_object.hh"
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43 44using namespace std; 45 46static uint8_t 47bcdize(uint8_t val) 48{ 49 uint8_t result; 50 result = val % 10; 51 result += (val / 10) << 4; 52 return result; 53} 54 55static uint8_t 56unbcdize(uint8_t val) 57{ 58 uint8_t result; 59 result = val & 0xf; 60 result += (val >> 4) * 10; 61 return result; 62} 63 64void 65MC146818::setTime(const struct tm time) 66{ 67 curTime = time; 68 year = time.tm_year; 69 // Unix is 0-11 for month, data seet says start at 1 70 mon = time.tm_mon + 1; 71 mday = time.tm_mday; 72 hour = time.tm_hour; 73 min = time.tm_min; 74 sec = time.tm_sec; 75 76 // Datasheet says 1 is sunday 77 wday = time.tm_wday + 1; 78 79 if (!(stat_regB & RTCB_BIN)) { 80 // The datasheet says that the year field can be either BCD or 81 // years since 1900. Linux seems to be happy with years since 82 // 1900. 83 year = bcdize(year % 100); 84 mon = bcdize(mon); 85 mday = bcdize(mday); 86 hour = bcdize(hour); 87 min = bcdize(min); 88 sec = bcdize(sec); 89 } 90} 91 92MC146818::MC146818(EventManager *em, const string &n, const struct tm time, 93 bool bcd, Tick frequency) 94 : EventManager(em), _name(n), event(this, frequency), tickEvent(this) 95{ 96 memset(clock_data, 0, sizeof(clock_data)); 97 stat_regA = RTCA_32768HZ | RTCA_1024HZ; 98 stat_regB = RTCB_PRDC_IE | RTCB_24HR; 99 if (!bcd) 100 stat_regB |= RTCB_BIN; 101 102 setTime(time); 103 DPRINTFN("Real-time clock set to %s", asctime(&time)); 104} 105 106MC146818::~MC146818() 107{
| 44 45using namespace std; 46 47static uint8_t 48bcdize(uint8_t val) 49{ 50 uint8_t result; 51 result = val % 10; 52 result += (val / 10) << 4; 53 return result; 54} 55 56static uint8_t 57unbcdize(uint8_t val) 58{ 59 uint8_t result; 60 result = val & 0xf; 61 result += (val >> 4) * 10; 62 return result; 63} 64 65void 66MC146818::setTime(const struct tm time) 67{ 68 curTime = time; 69 year = time.tm_year; 70 // Unix is 0-11 for month, data seet says start at 1 71 mon = time.tm_mon + 1; 72 mday = time.tm_mday; 73 hour = time.tm_hour; 74 min = time.tm_min; 75 sec = time.tm_sec; 76 77 // Datasheet says 1 is sunday 78 wday = time.tm_wday + 1; 79 80 if (!(stat_regB & RTCB_BIN)) { 81 // The datasheet says that the year field can be either BCD or 82 // years since 1900. Linux seems to be happy with years since 83 // 1900. 84 year = bcdize(year % 100); 85 mon = bcdize(mon); 86 mday = bcdize(mday); 87 hour = bcdize(hour); 88 min = bcdize(min); 89 sec = bcdize(sec); 90 } 91} 92 93MC146818::MC146818(EventManager *em, const string &n, const struct tm time, 94 bool bcd, Tick frequency) 95 : EventManager(em), _name(n), event(this, frequency), tickEvent(this) 96{ 97 memset(clock_data, 0, sizeof(clock_data)); 98 stat_regA = RTCA_32768HZ | RTCA_1024HZ; 99 stat_regB = RTCB_PRDC_IE | RTCB_24HR; 100 if (!bcd) 101 stat_regB |= RTCB_BIN; 102 103 setTime(time); 104 DPRINTFN("Real-time clock set to %s", asctime(&time)); 105} 106 107MC146818::~MC146818() 108{
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108 deschedule(tickEvent); 109 deschedule(event);
| 109 if (tickEvent.scheduled()) { 110 deschedule(tickEvent); 111 } 112 if (event.scheduled()) { 113 deschedule(event); 114 }
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110} 111 112void 113MC146818::writeData(const uint8_t addr, const uint8_t data) 114{ 115 if (addr < RTC_STAT_REGA) { 116 clock_data[addr] = data; 117 curTime.tm_sec = unbcdize(sec); 118 curTime.tm_min = unbcdize(min); 119 curTime.tm_hour = unbcdize(hour); 120 curTime.tm_mday = unbcdize(mday); 121 curTime.tm_mon = unbcdize(mon) - 1; 122 curTime.tm_year = ((unbcdize(year) + 50) % 100) + 1950; 123 curTime.tm_wday = unbcdize(wday) - 1; 124 } else { 125 switch (addr) { 126 case RTC_STAT_REGA: 127 // The "update in progress" bit is read only. 128 if ((data & ~RTCA_UIP) != (RTCA_32768HZ | RTCA_1024HZ)) 129 panic("Unimplemented RTC register A value write!\n"); 130 replaceBits(stat_regA, data, 6, 0); 131 break; 132 case RTC_STAT_REGB: 133 if ((data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != RTCB_24HR) 134 panic("Write to RTC reg B bits that are not implemented!\n"); 135 136 if (data & RTCB_PRDC_IE) { 137 if (!event.scheduled()) 138 event.scheduleIntr(); 139 } else { 140 if (event.scheduled()) 141 deschedule(event); 142 } 143 stat_regB = data; 144 break; 145 case RTC_STAT_REGC: 146 case RTC_STAT_REGD: 147 panic("RTC status registers C and D are not implemented.\n"); 148 break; 149 } 150 } 151} 152 153uint8_t 154MC146818::readData(uint8_t addr) 155{ 156 if (addr < RTC_STAT_REGA) 157 return clock_data[addr]; 158 else { 159 switch (addr) { 160 case RTC_STAT_REGA: 161 // toggle UIP bit for linux 162 stat_regA ^= RTCA_UIP; 163 return stat_regA; 164 break; 165 case RTC_STAT_REGB: 166 return stat_regB; 167 break; 168 case RTC_STAT_REGC: 169 case RTC_STAT_REGD: 170 return 0x00; 171 break; 172 default: 173 panic("Shouldn't be here"); 174 } 175 } 176} 177 178static time_t 179mkutctime(struct tm *time) 180{ 181 time_t ret; 182 char *tz; 183 184 tz = getenv("TZ"); 185 setenv("TZ", "", 1); 186 tzset(); 187 ret = mktime(time); 188 if (tz) 189 setenv("TZ", tz, 1); 190 else 191 unsetenv("TZ"); 192 tzset(); 193 return ret; 194} 195 196void 197MC146818::tickClock() 198{ 199 if (stat_regB & RTCB_NO_UPDT) 200 return; 201 time_t calTime = mkutctime(&curTime); 202 calTime++; 203 setTime(*gmtime(&calTime)); 204} 205
| 115} 116 117void 118MC146818::writeData(const uint8_t addr, const uint8_t data) 119{ 120 if (addr < RTC_STAT_REGA) { 121 clock_data[addr] = data; 122 curTime.tm_sec = unbcdize(sec); 123 curTime.tm_min = unbcdize(min); 124 curTime.tm_hour = unbcdize(hour); 125 curTime.tm_mday = unbcdize(mday); 126 curTime.tm_mon = unbcdize(mon) - 1; 127 curTime.tm_year = ((unbcdize(year) + 50) % 100) + 1950; 128 curTime.tm_wday = unbcdize(wday) - 1; 129 } else { 130 switch (addr) { 131 case RTC_STAT_REGA: 132 // The "update in progress" bit is read only. 133 if ((data & ~RTCA_UIP) != (RTCA_32768HZ | RTCA_1024HZ)) 134 panic("Unimplemented RTC register A value write!\n"); 135 replaceBits(stat_regA, data, 6, 0); 136 break; 137 case RTC_STAT_REGB: 138 if ((data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != RTCB_24HR) 139 panic("Write to RTC reg B bits that are not implemented!\n"); 140 141 if (data & RTCB_PRDC_IE) { 142 if (!event.scheduled()) 143 event.scheduleIntr(); 144 } else { 145 if (event.scheduled()) 146 deschedule(event); 147 } 148 stat_regB = data; 149 break; 150 case RTC_STAT_REGC: 151 case RTC_STAT_REGD: 152 panic("RTC status registers C and D are not implemented.\n"); 153 break; 154 } 155 } 156} 157 158uint8_t 159MC146818::readData(uint8_t addr) 160{ 161 if (addr < RTC_STAT_REGA) 162 return clock_data[addr]; 163 else { 164 switch (addr) { 165 case RTC_STAT_REGA: 166 // toggle UIP bit for linux 167 stat_regA ^= RTCA_UIP; 168 return stat_regA; 169 break; 170 case RTC_STAT_REGB: 171 return stat_regB; 172 break; 173 case RTC_STAT_REGC: 174 case RTC_STAT_REGD: 175 return 0x00; 176 break; 177 default: 178 panic("Shouldn't be here"); 179 } 180 } 181} 182 183static time_t 184mkutctime(struct tm *time) 185{ 186 time_t ret; 187 char *tz; 188 189 tz = getenv("TZ"); 190 setenv("TZ", "", 1); 191 tzset(); 192 ret = mktime(time); 193 if (tz) 194 setenv("TZ", tz, 1); 195 else 196 unsetenv("TZ"); 197 tzset(); 198 return ret; 199} 200 201void 202MC146818::tickClock() 203{ 204 if (stat_regB & RTCB_NO_UPDT) 205 return; 206 time_t calTime = mkutctime(&curTime); 207 calTime++; 208 setTime(*gmtime(&calTime)); 209} 210
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| 211unsigned int 212MC146818::drain(Event *de) 213{ 214 if (event.scheduled()) { 215 rtcTimerInterruptTickOffset = event.when() - curTick; 216 rtcClockTickOffset = event.when() - curTick; 217 deschedule(event); 218 } 219 if (tickEvent.scheduled()) { 220 deschedule(tickEvent); 221 } 222 return 0; 223} 224
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206void 207MC146818::serialize(const string &base, ostream &os) 208{ 209 arrayParamOut(os, base + ".clock_data", clock_data, sizeof(clock_data)); 210 paramOut(os, base + ".stat_regA", stat_regA); 211 paramOut(os, base + ".stat_regB", stat_regB); 212 213 // 214 // save the timer tick and rtc clock tick values to correctly reschedule 215 // them during unserialize 216 //
| 225void 226MC146818::serialize(const string &base, ostream &os) 227{ 228 arrayParamOut(os, base + ".clock_data", clock_data, sizeof(clock_data)); 229 paramOut(os, base + ".stat_regA", stat_regA); 230 paramOut(os, base + ".stat_regB", stat_regB); 231 232 // 233 // save the timer tick and rtc clock tick values to correctly reschedule 234 // them during unserialize 235 //
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217 Tick rtcTimerInterruptTickOffset = event.when() - curTick;
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218 SERIALIZE_SCALAR(rtcTimerInterruptTickOffset);
| 236 SERIALIZE_SCALAR(rtcTimerInterruptTickOffset);
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219 Tick rtcClockTickOffset = event.when() - curTick;
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220 SERIALIZE_SCALAR(rtcClockTickOffset); 221} 222 223void 224MC146818::unserialize(const string &base, Checkpoint *cp, 225 const string §ion) 226{ 227 arrayParamIn(cp, section, base + ".clock_data", clock_data, 228 sizeof(clock_data)); 229 paramIn(cp, section, base + ".stat_regA", stat_regA); 230 paramIn(cp, section, base + ".stat_regB", stat_regB); 231 232 // 233 // properly schedule the timer and rtc clock events 234 // 235 Tick rtcTimerInterruptTickOffset; 236 UNSERIALIZE_SCALAR(rtcTimerInterruptTickOffset); 237 reschedule(event, curTick + rtcTimerInterruptTickOffset); 238 Tick rtcClockTickOffset; 239 UNSERIALIZE_SCALAR(rtcClockTickOffset); 240 reschedule(tickEvent, curTick + rtcClockTickOffset); 241} 242 243MC146818::RTCEvent::RTCEvent(MC146818 * _parent, Tick i) 244 : parent(_parent), interval(i) 245{ 246 DPRINTF(MC146818, "RTC Event Initilizing\n"); 247 parent->schedule(this, curTick + interval); 248} 249 250void 251MC146818::RTCEvent::scheduleIntr() 252{ 253 parent->schedule(this, curTick + interval); 254} 255 256void 257MC146818::RTCEvent::process() 258{ 259 DPRINTF(MC146818, "RTC Timer Interrupt\n"); 260 parent->schedule(this, curTick + interval); 261 parent->handleEvent(); 262} 263 264const char * 265MC146818::RTCEvent::description() const 266{ 267 return "RTC interrupt"; 268} 269 270void 271MC146818::RTCTickEvent::process() 272{ 273 DPRINTF(MC146818, "RTC clock tick\n"); 274 parent->schedule(this, curTick + SimClock::Int::s); 275 parent->tickClock(); 276} 277 278const char * 279MC146818::RTCTickEvent::description() const 280{ 281 return "RTC clock tick"; 282}
| 237 SERIALIZE_SCALAR(rtcClockTickOffset); 238} 239 240void 241MC146818::unserialize(const string &base, Checkpoint *cp, 242 const string §ion) 243{ 244 arrayParamIn(cp, section, base + ".clock_data", clock_data, 245 sizeof(clock_data)); 246 paramIn(cp, section, base + ".stat_regA", stat_regA); 247 paramIn(cp, section, base + ".stat_regB", stat_regB); 248 249 // 250 // properly schedule the timer and rtc clock events 251 // 252 Tick rtcTimerInterruptTickOffset; 253 UNSERIALIZE_SCALAR(rtcTimerInterruptTickOffset); 254 reschedule(event, curTick + rtcTimerInterruptTickOffset); 255 Tick rtcClockTickOffset; 256 UNSERIALIZE_SCALAR(rtcClockTickOffset); 257 reschedule(tickEvent, curTick + rtcClockTickOffset); 258} 259 260MC146818::RTCEvent::RTCEvent(MC146818 * _parent, Tick i) 261 : parent(_parent), interval(i) 262{ 263 DPRINTF(MC146818, "RTC Event Initilizing\n"); 264 parent->schedule(this, curTick + interval); 265} 266 267void 268MC146818::RTCEvent::scheduleIntr() 269{ 270 parent->schedule(this, curTick + interval); 271} 272 273void 274MC146818::RTCEvent::process() 275{ 276 DPRINTF(MC146818, "RTC Timer Interrupt\n"); 277 parent->schedule(this, curTick + interval); 278 parent->handleEvent(); 279} 280 281const char * 282MC146818::RTCEvent::description() const 283{ 284 return "RTC interrupt"; 285} 286 287void 288MC146818::RTCTickEvent::process() 289{ 290 DPRINTF(MC146818, "RTC clock tick\n"); 291 parent->schedule(this, curTick + SimClock::Int::s); 292 parent->tickClock(); 293} 294 295const char * 296MC146818::RTCTickEvent::description() const 297{ 298 return "RTC clock tick"; 299}
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