1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Andrew Schultz
30 * Miguel Serrano
31 */
32
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Andrew Schultz
30 * Miguel Serrano
31 */
32
|
43#include "dev/rtcreg.h"
44
45using namespace std;
46
47static uint8_t
48bcdize(uint8_t val)
49{
50 uint8_t result;
51 result = val % 10;
52 result += (val / 10) << 4;
53 return result;
54}
55
56static uint8_t
57unbcdize(uint8_t val)
58{
59 uint8_t result;
60 result = val & 0xf;
61 result += (val >> 4) * 10;
62 return result;
63}
64
65void
66MC146818::setTime(const struct tm time)
67{
68 curTime = time;
69 year = time.tm_year;
70 // Unix is 0-11 for month, data seet says start at 1
71 mon = time.tm_mon + 1;
72 mday = time.tm_mday;
73 hour = time.tm_hour;
74 min = time.tm_min;
75 sec = time.tm_sec;
76
77 // Datasheet says 1 is sunday
78 wday = time.tm_wday + 1;
79
80 if (!stat_regB.dm) {
81 // The datasheet says that the year field can be either BCD or
82 // years since 1900. Linux seems to be happy with years since
83 // 1900.
84 year = bcdize(year % 100);
85 mon = bcdize(mon);
86 mday = bcdize(mday);
87 hour = bcdize(hour);
88 min = bcdize(min);
89 sec = bcdize(sec);
90 }
91}
92
93MC146818::MC146818(EventManager *em, const string &n, const struct tm time,
94 bool bcd, Tick frequency)
95 : EventManager(em), _name(n), event(this, frequency), tickEvent(this)
96{
97 memset(clock_data, 0, sizeof(clock_data));
98
99 stat_regA = 0;
100 stat_regA.dv = RTCA_DV_32768HZ;
101 stat_regA.rs = RTCA_RS_1024HZ;
102
103 stat_regB = 0;
104 stat_regB.pie = 1;
105 stat_regB.format24h = 1;
106 stat_regB.dm = bcd ? 0 : 1;
107
108 setTime(time);
109 DPRINTFN("Real-time clock set to %s", asctime(&time));
110}
111
112MC146818::~MC146818()
113{
114 deschedule(tickEvent);
115 deschedule(event);
116}
117
118bool
119MC146818::rega_dv_disabled(const RtcRegA ®)
120{
121 return reg.dv == RTCA_DV_DISABLED0 ||
122 reg.dv == RTCA_DV_DISABLED1;
123}
124
125void
126MC146818::startup()
127{
128 assert(!event.scheduled());
129 assert(!tickEvent.scheduled());
130
131 if (stat_regB.pie)
132 schedule(event, curTick() + event.offset);
133 if (!rega_dv_disabled(stat_regA))
134 schedule(tickEvent, curTick() + tickEvent.offset);
135}
136
137void
138MC146818::writeData(const uint8_t addr, const uint8_t data)
139{
140 bool panic_unsupported(false);
141
142 if (addr < RTC_STAT_REGA) {
143 clock_data[addr] = data;
144 curTime.tm_sec = unbcdize(sec);
145 curTime.tm_min = unbcdize(min);
146 curTime.tm_hour = unbcdize(hour);
147 curTime.tm_mday = unbcdize(mday);
148 curTime.tm_mon = unbcdize(mon) - 1;
149 curTime.tm_year = ((unbcdize(year) + 50) % 100) + 1950;
150 curTime.tm_wday = unbcdize(wday) - 1;
151 } else {
152 switch (addr) {
153 case RTC_STAT_REGA: {
154 RtcRegA old_rega(stat_regA);
155 stat_regA = data;
156 // The "update in progress" bit is read only.
157 stat_regA.uip = old_rega;
158
159 if (!rega_dv_disabled(stat_regA) &&
160 stat_regA.dv != RTCA_DV_32768HZ) {
161 inform("RTC: Unimplemented divider configuration: %i\n",
162 stat_regA.dv);
163 panic_unsupported = true;
164 }
165
166 if (stat_regA.rs != RTCA_RS_1024HZ) {
167 inform("RTC: Unimplemented interrupt rate: %i\n",
168 stat_regA.rs);
169 panic_unsupported = true;
170 }
171
172 if (rega_dv_disabled(stat_regA)) {
173 // The divider is disabled, make sure that we don't
174 // schedule any ticks.
175 if (tickEvent.scheduled())
176 deschedule(tickEvent);
177 } else if (rega_dv_disabled(old_rega)) {
178 // According to the specification, the next tick
179 // happens after 0.5s when the divider chain goes
180 // from reset to active. So, we simply schedule the
181 // tick after 0.5s.
182 assert(!tickEvent.scheduled());
183 schedule(tickEvent, curTick() + SimClock::Int::s / 2);
184 }
185 } break;
186 case RTC_STAT_REGB:
187 stat_regB = data;
188 if (stat_regB.aie || stat_regB.uie) {
189 inform("RTC: Unimplemented interrupt configuration: %s %s\n",
190 stat_regB.aie ? "alarm" : "",
191 stat_regB.uie ? "update" : "");
192 panic_unsupported = true;
193 }
194
195 if (stat_regB.dm) {
196 inform("RTC: The binary interface is not fully implemented.\n");
197 panic_unsupported = true;
198 }
199
200 if (!stat_regB.format24h) {
201 inform("RTC: The 12h time format not supported.\n");
202 panic_unsupported = true;
203 }
204
205 if (stat_regB.dse) {
206 inform("RTC: Automatic daylight saving time not supported.\n");
207 panic_unsupported = true;
208 }
209
210 if (stat_regB.pie) {
211 if (!event.scheduled())
212 event.scheduleIntr();
213 } else {
214 if (event.scheduled())
215 deschedule(event);
216 }
217 break;
218 case RTC_STAT_REGC:
219 case RTC_STAT_REGD:
220 panic("RTC status registers C and D are not implemented.\n");
221 break;
222 }
223 }
224
225 if (panic_unsupported)
226 panic("Unimplemented RTC configuration!\n");
227
228}
229
230uint8_t
231MC146818::readData(uint8_t addr)
232{
233 if (addr < RTC_STAT_REGA)
234 return clock_data[addr];
235 else {
236 switch (addr) {
237 case RTC_STAT_REGA:
238 // toggle UIP bit for linux
239 stat_regA.uip = !stat_regA.uip;
240 return stat_regA;
241 break;
242 case RTC_STAT_REGB:
243 return stat_regB;
244 break;
245 case RTC_STAT_REGC:
246 case RTC_STAT_REGD:
247 return 0x00;
248 break;
249 default:
250 panic("Shouldn't be here");
251 }
252 }
253}
254
255void
256MC146818::tickClock()
257{
258 assert(!rega_dv_disabled(stat_regA));
259
260 if (stat_regB.set)
261 return;
262 time_t calTime = mkutctime(&curTime);
263 calTime++;
264 setTime(*gmtime(&calTime));
265}
266
267void
268MC146818::serialize(const string &base, CheckpointOut &cp) const
269{
270 uint8_t regA_serial(stat_regA);
271 uint8_t regB_serial(stat_regB);
272
273 arrayParamOut(cp, base + ".clock_data", clock_data, sizeof(clock_data));
274 paramOut(cp, base + ".stat_regA", (uint8_t)regA_serial);
275 paramOut(cp, base + ".stat_regB", (uint8_t)regB_serial);
276
277 //
278 // save the timer tick and rtc clock tick values to correctly reschedule
279 // them during unserialize
280 //
281 Tick rtcTimerInterruptTickOffset = event.when() - curTick();
282 SERIALIZE_SCALAR(rtcTimerInterruptTickOffset);
283 Tick rtcClockTickOffset = tickEvent.when() - curTick();
284 SERIALIZE_SCALAR(rtcClockTickOffset);
285}
286
287void
288MC146818::unserialize(const string &base, CheckpointIn &cp)
289{
290 uint8_t tmp8;
291
292 arrayParamIn(cp, base + ".clock_data", clock_data,
293 sizeof(clock_data));
294
295 paramIn(cp, base + ".stat_regA", tmp8);
296 stat_regA = tmp8;
297 paramIn(cp, base + ".stat_regB", tmp8);
298 stat_regB = tmp8;
299
300 //
301 // properly schedule the timer and rtc clock events
302 //
303 Tick rtcTimerInterruptTickOffset;
304 UNSERIALIZE_SCALAR(rtcTimerInterruptTickOffset);
305 event.offset = rtcTimerInterruptTickOffset;
306 Tick rtcClockTickOffset;
307 UNSERIALIZE_SCALAR(rtcClockTickOffset);
308 tickEvent.offset = rtcClockTickOffset;
309}
310
311MC146818::RTCEvent::RTCEvent(MC146818 * _parent, Tick i)
312 : parent(_parent), interval(i), offset(i)
313{
314 DPRINTF(MC146818, "RTC Event Initilizing\n");
315}
316
317void
318MC146818::RTCEvent::scheduleIntr()
319{
320 parent->schedule(this, curTick() + interval);
321}
322
323void
324MC146818::RTCEvent::process()
325{
326 DPRINTF(MC146818, "RTC Timer Interrupt\n");
327 parent->schedule(this, curTick() + interval);
328 parent->handleEvent();
329}
330
331const char *
332MC146818::RTCEvent::description() const
333{
334 return "RTC interrupt";
335}
336
337void
338MC146818::RTCTickEvent::process()
339{
340 DPRINTF(MC146818, "RTC clock tick\n");
341 parent->schedule(this, curTick() + SimClock::Int::s);
342 parent->tickClock();
343}
344
345const char *
346MC146818::RTCTickEvent::description() const
347{
348 return "RTC clock tick";
349}
| 44#include "dev/rtcreg.h"
45
46using namespace std;
47
48static uint8_t
49bcdize(uint8_t val)
50{
51 uint8_t result;
52 result = val % 10;
53 result += (val / 10) << 4;
54 return result;
55}
56
57static uint8_t
58unbcdize(uint8_t val)
59{
60 uint8_t result;
61 result = val & 0xf;
62 result += (val >> 4) * 10;
63 return result;
64}
65
66void
67MC146818::setTime(const struct tm time)
68{
69 curTime = time;
70 year = time.tm_year;
71 // Unix is 0-11 for month, data seet says start at 1
72 mon = time.tm_mon + 1;
73 mday = time.tm_mday;
74 hour = time.tm_hour;
75 min = time.tm_min;
76 sec = time.tm_sec;
77
78 // Datasheet says 1 is sunday
79 wday = time.tm_wday + 1;
80
81 if (!stat_regB.dm) {
82 // The datasheet says that the year field can be either BCD or
83 // years since 1900. Linux seems to be happy with years since
84 // 1900.
85 year = bcdize(year % 100);
86 mon = bcdize(mon);
87 mday = bcdize(mday);
88 hour = bcdize(hour);
89 min = bcdize(min);
90 sec = bcdize(sec);
91 }
92}
93
94MC146818::MC146818(EventManager *em, const string &n, const struct tm time,
95 bool bcd, Tick frequency)
96 : EventManager(em), _name(n), event(this, frequency), tickEvent(this)
97{
98 memset(clock_data, 0, sizeof(clock_data));
99
100 stat_regA = 0;
101 stat_regA.dv = RTCA_DV_32768HZ;
102 stat_regA.rs = RTCA_RS_1024HZ;
103
104 stat_regB = 0;
105 stat_regB.pie = 1;
106 stat_regB.format24h = 1;
107 stat_regB.dm = bcd ? 0 : 1;
108
109 setTime(time);
110 DPRINTFN("Real-time clock set to %s", asctime(&time));
111}
112
113MC146818::~MC146818()
114{
115 deschedule(tickEvent);
116 deschedule(event);
117}
118
119bool
120MC146818::rega_dv_disabled(const RtcRegA ®)
121{
122 return reg.dv == RTCA_DV_DISABLED0 ||
123 reg.dv == RTCA_DV_DISABLED1;
124}
125
126void
127MC146818::startup()
128{
129 assert(!event.scheduled());
130 assert(!tickEvent.scheduled());
131
132 if (stat_regB.pie)
133 schedule(event, curTick() + event.offset);
134 if (!rega_dv_disabled(stat_regA))
135 schedule(tickEvent, curTick() + tickEvent.offset);
136}
137
138void
139MC146818::writeData(const uint8_t addr, const uint8_t data)
140{
141 bool panic_unsupported(false);
142
143 if (addr < RTC_STAT_REGA) {
144 clock_data[addr] = data;
145 curTime.tm_sec = unbcdize(sec);
146 curTime.tm_min = unbcdize(min);
147 curTime.tm_hour = unbcdize(hour);
148 curTime.tm_mday = unbcdize(mday);
149 curTime.tm_mon = unbcdize(mon) - 1;
150 curTime.tm_year = ((unbcdize(year) + 50) % 100) + 1950;
151 curTime.tm_wday = unbcdize(wday) - 1;
152 } else {
153 switch (addr) {
154 case RTC_STAT_REGA: {
155 RtcRegA old_rega(stat_regA);
156 stat_regA = data;
157 // The "update in progress" bit is read only.
158 stat_regA.uip = old_rega;
159
160 if (!rega_dv_disabled(stat_regA) &&
161 stat_regA.dv != RTCA_DV_32768HZ) {
162 inform("RTC: Unimplemented divider configuration: %i\n",
163 stat_regA.dv);
164 panic_unsupported = true;
165 }
166
167 if (stat_regA.rs != RTCA_RS_1024HZ) {
168 inform("RTC: Unimplemented interrupt rate: %i\n",
169 stat_regA.rs);
170 panic_unsupported = true;
171 }
172
173 if (rega_dv_disabled(stat_regA)) {
174 // The divider is disabled, make sure that we don't
175 // schedule any ticks.
176 if (tickEvent.scheduled())
177 deschedule(tickEvent);
178 } else if (rega_dv_disabled(old_rega)) {
179 // According to the specification, the next tick
180 // happens after 0.5s when the divider chain goes
181 // from reset to active. So, we simply schedule the
182 // tick after 0.5s.
183 assert(!tickEvent.scheduled());
184 schedule(tickEvent, curTick() + SimClock::Int::s / 2);
185 }
186 } break;
187 case RTC_STAT_REGB:
188 stat_regB = data;
189 if (stat_regB.aie || stat_regB.uie) {
190 inform("RTC: Unimplemented interrupt configuration: %s %s\n",
191 stat_regB.aie ? "alarm" : "",
192 stat_regB.uie ? "update" : "");
193 panic_unsupported = true;
194 }
195
196 if (stat_regB.dm) {
197 inform("RTC: The binary interface is not fully implemented.\n");
198 panic_unsupported = true;
199 }
200
201 if (!stat_regB.format24h) {
202 inform("RTC: The 12h time format not supported.\n");
203 panic_unsupported = true;
204 }
205
206 if (stat_regB.dse) {
207 inform("RTC: Automatic daylight saving time not supported.\n");
208 panic_unsupported = true;
209 }
210
211 if (stat_regB.pie) {
212 if (!event.scheduled())
213 event.scheduleIntr();
214 } else {
215 if (event.scheduled())
216 deschedule(event);
217 }
218 break;
219 case RTC_STAT_REGC:
220 case RTC_STAT_REGD:
221 panic("RTC status registers C and D are not implemented.\n");
222 break;
223 }
224 }
225
226 if (panic_unsupported)
227 panic("Unimplemented RTC configuration!\n");
228
229}
230
231uint8_t
232MC146818::readData(uint8_t addr)
233{
234 if (addr < RTC_STAT_REGA)
235 return clock_data[addr];
236 else {
237 switch (addr) {
238 case RTC_STAT_REGA:
239 // toggle UIP bit for linux
240 stat_regA.uip = !stat_regA.uip;
241 return stat_regA;
242 break;
243 case RTC_STAT_REGB:
244 return stat_regB;
245 break;
246 case RTC_STAT_REGC:
247 case RTC_STAT_REGD:
248 return 0x00;
249 break;
250 default:
251 panic("Shouldn't be here");
252 }
253 }
254}
255
256void
257MC146818::tickClock()
258{
259 assert(!rega_dv_disabled(stat_regA));
260
261 if (stat_regB.set)
262 return;
263 time_t calTime = mkutctime(&curTime);
264 calTime++;
265 setTime(*gmtime(&calTime));
266}
267
268void
269MC146818::serialize(const string &base, CheckpointOut &cp) const
270{
271 uint8_t regA_serial(stat_regA);
272 uint8_t regB_serial(stat_regB);
273
274 arrayParamOut(cp, base + ".clock_data", clock_data, sizeof(clock_data));
275 paramOut(cp, base + ".stat_regA", (uint8_t)regA_serial);
276 paramOut(cp, base + ".stat_regB", (uint8_t)regB_serial);
277
278 //
279 // save the timer tick and rtc clock tick values to correctly reschedule
280 // them during unserialize
281 //
282 Tick rtcTimerInterruptTickOffset = event.when() - curTick();
283 SERIALIZE_SCALAR(rtcTimerInterruptTickOffset);
284 Tick rtcClockTickOffset = tickEvent.when() - curTick();
285 SERIALIZE_SCALAR(rtcClockTickOffset);
286}
287
288void
289MC146818::unserialize(const string &base, CheckpointIn &cp)
290{
291 uint8_t tmp8;
292
293 arrayParamIn(cp, base + ".clock_data", clock_data,
294 sizeof(clock_data));
295
296 paramIn(cp, base + ".stat_regA", tmp8);
297 stat_regA = tmp8;
298 paramIn(cp, base + ".stat_regB", tmp8);
299 stat_regB = tmp8;
300
301 //
302 // properly schedule the timer and rtc clock events
303 //
304 Tick rtcTimerInterruptTickOffset;
305 UNSERIALIZE_SCALAR(rtcTimerInterruptTickOffset);
306 event.offset = rtcTimerInterruptTickOffset;
307 Tick rtcClockTickOffset;
308 UNSERIALIZE_SCALAR(rtcClockTickOffset);
309 tickEvent.offset = rtcClockTickOffset;
310}
311
312MC146818::RTCEvent::RTCEvent(MC146818 * _parent, Tick i)
313 : parent(_parent), interval(i), offset(i)
314{
315 DPRINTF(MC146818, "RTC Event Initilizing\n");
316}
317
318void
319MC146818::RTCEvent::scheduleIntr()
320{
321 parent->schedule(this, curTick() + interval);
322}
323
324void
325MC146818::RTCEvent::process()
326{
327 DPRINTF(MC146818, "RTC Timer Interrupt\n");
328 parent->schedule(this, curTick() + interval);
329 parent->handleEvent();
330}
331
332const char *
333MC146818::RTCEvent::description() const
334{
335 return "RTC interrupt";
336}
337
338void
339MC146818::RTCTickEvent::process()
340{
341 DPRINTF(MC146818, "RTC clock tick\n");
342 parent->schedule(this, curTick() + SimClock::Int::s);
343 parent->tickClock();
344}
345
346const char *
347MC146818::RTCTickEvent::description() const
348{
349 return "RTC clock tick";
350}
|