1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Andrew Schultz
30 * Miguel Serrano
31 */
32
33#include <sys/time.h>
34
35#include <ctime>
36#include <string>
37
38#include "base/bitfield.hh"
39#include "base/time.hh"
40#include "base/trace.hh"
41#include "debug/MC146818.hh"
42#include "dev/mc146818.hh"
43#include "dev/rtcreg.h"
44
45using namespace std;
46
47static uint8_t
48bcdize(uint8_t val)
49{
50 uint8_t result;
51 result = val % 10;
52 result += (val / 10) << 4;
53 return result;
54}
55
56static uint8_t
57unbcdize(uint8_t val)
58{
59 uint8_t result;
60 result = val & 0xf;
61 result += (val >> 4) * 10;
62 return result;
63}
64
65void
66MC146818::setTime(const struct tm time)
67{
68 curTime = time;
69 year = time.tm_year;
70 // Unix is 0-11 for month, data seet says start at 1
71 mon = time.tm_mon + 1;
72 mday = time.tm_mday;
73 hour = time.tm_hour;
74 min = time.tm_min;
75 sec = time.tm_sec;
76
77 // Datasheet says 1 is sunday
78 wday = time.tm_wday + 1;
79
80 if (!stat_regB.dm) {
81 // The datasheet says that the year field can be either BCD or
82 // years since 1900. Linux seems to be happy with years since
83 // 1900.
84 year = bcdize(year % 100);
85 mon = bcdize(mon);
86 mday = bcdize(mday);
87 hour = bcdize(hour);
88 min = bcdize(min);
89 sec = bcdize(sec);
90 }
91}
92
93MC146818::MC146818(EventManager *em, const string &n, const struct tm time,
94 bool bcd, Tick frequency)
95 : EventManager(em), _name(n), event(this, frequency), tickEvent(this)
96{
97 memset(clock_data, 0, sizeof(clock_data));
98
99 stat_regA = 0;
100 stat_regA.dv = RTCA_DV_32768HZ;
101 stat_regA.rs = RTCA_RS_1024HZ;
102
103 stat_regB = 0;
104 stat_regB.pie = 1;
105 stat_regB.format24h = 1;
106 stat_regB.dm = bcd ? 0 : 1;
107
108 setTime(time);
109 DPRINTFN("Real-time clock set to %s", asctime(&time));
110}
111
112MC146818::~MC146818()
113{
114 deschedule(tickEvent);
115 deschedule(event);
116}
117
118bool
119MC146818::rega_dv_disabled(const RtcRegA ®)
120{
121 return reg.dv == RTCA_DV_DISABLED0 ||
122 reg.dv == RTCA_DV_DISABLED1;
123}
124
125void
126MC146818::startup()
127{
128 assert(!event.scheduled());
129 assert(!tickEvent.scheduled());
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Andrew Schultz
30 * Miguel Serrano
31 */
32
33#include <sys/time.h>
34
35#include <ctime>
36#include <string>
37
38#include "base/bitfield.hh"
39#include "base/time.hh"
40#include "base/trace.hh"
41#include "debug/MC146818.hh"
42#include "dev/mc146818.hh"
43#include "dev/rtcreg.h"
44
45using namespace std;
46
47static uint8_t
48bcdize(uint8_t val)
49{
50 uint8_t result;
51 result = val % 10;
52 result += (val / 10) << 4;
53 return result;
54}
55
56static uint8_t
57unbcdize(uint8_t val)
58{
59 uint8_t result;
60 result = val & 0xf;
61 result += (val >> 4) * 10;
62 return result;
63}
64
65void
66MC146818::setTime(const struct tm time)
67{
68 curTime = time;
69 year = time.tm_year;
70 // Unix is 0-11 for month, data seet says start at 1
71 mon = time.tm_mon + 1;
72 mday = time.tm_mday;
73 hour = time.tm_hour;
74 min = time.tm_min;
75 sec = time.tm_sec;
76
77 // Datasheet says 1 is sunday
78 wday = time.tm_wday + 1;
79
80 if (!stat_regB.dm) {
81 // The datasheet says that the year field can be either BCD or
82 // years since 1900. Linux seems to be happy with years since
83 // 1900.
84 year = bcdize(year % 100);
85 mon = bcdize(mon);
86 mday = bcdize(mday);
87 hour = bcdize(hour);
88 min = bcdize(min);
89 sec = bcdize(sec);
90 }
91}
92
93MC146818::MC146818(EventManager *em, const string &n, const struct tm time,
94 bool bcd, Tick frequency)
95 : EventManager(em), _name(n), event(this, frequency), tickEvent(this)
96{
97 memset(clock_data, 0, sizeof(clock_data));
98
99 stat_regA = 0;
100 stat_regA.dv = RTCA_DV_32768HZ;
101 stat_regA.rs = RTCA_RS_1024HZ;
102
103 stat_regB = 0;
104 stat_regB.pie = 1;
105 stat_regB.format24h = 1;
106 stat_regB.dm = bcd ? 0 : 1;
107
108 setTime(time);
109 DPRINTFN("Real-time clock set to %s", asctime(&time));
110}
111
112MC146818::~MC146818()
113{
114 deschedule(tickEvent);
115 deschedule(event);
116}
117
118bool
119MC146818::rega_dv_disabled(const RtcRegA ®)
120{
121 return reg.dv == RTCA_DV_DISABLED0 ||
122 reg.dv == RTCA_DV_DISABLED1;
123}
124
125void
126MC146818::startup()
127{
128 assert(!event.scheduled());
129 assert(!tickEvent.scheduled());
|
132}
133
134void
135MC146818::writeData(const uint8_t addr, const uint8_t data)
136{
137 bool panic_unsupported(false);
138
139 if (addr < RTC_STAT_REGA) {
140 clock_data[addr] = data;
141 curTime.tm_sec = unbcdize(sec);
142 curTime.tm_min = unbcdize(min);
143 curTime.tm_hour = unbcdize(hour);
144 curTime.tm_mday = unbcdize(mday);
145 curTime.tm_mon = unbcdize(mon) - 1;
146 curTime.tm_year = ((unbcdize(year) + 50) % 100) + 1950;
147 curTime.tm_wday = unbcdize(wday) - 1;
148 } else {
149 switch (addr) {
150 case RTC_STAT_REGA: {
151 RtcRegA old_rega(stat_regA);
152 stat_regA = data;
153 // The "update in progress" bit is read only.
154 stat_regA.uip = old_rega;
155
156 if (!rega_dv_disabled(stat_regA) &&
157 stat_regA.dv != RTCA_DV_32768HZ) {
158 inform("RTC: Unimplemented divider configuration: %i\n",
159 stat_regA.dv);
160 panic_unsupported = true;
161 }
162
163 if (stat_regA.rs != RTCA_RS_1024HZ) {
164 inform("RTC: Unimplemented interrupt rate: %i\n",
165 stat_regA.rs);
166 panic_unsupported = true;
167 }
168
169 if (rega_dv_disabled(stat_regA)) {
170 // The divider is disabled, make sure that we don't
171 // schedule any ticks.
172 if (tickEvent.scheduled())
173 deschedule(tickEvent);
174 } else if (rega_dv_disabled(old_rega)) {
175 // According to the specification, the next tick
176 // happens after 0.5s when the divider chain goes
177 // from reset to active. So, we simply schedule the
178 // tick after 0.5s.
179 assert(!tickEvent.scheduled());
180 schedule(tickEvent, curTick() + SimClock::Int::s / 2);
181 }
182 } break;
183 case RTC_STAT_REGB:
184 stat_regB = data;
185 if (stat_regB.aie || stat_regB.uie) {
186 inform("RTC: Unimplemented interrupt configuration: %s %s\n",
187 stat_regB.aie ? "alarm" : "",
188 stat_regB.uie ? "update" : "");
189 panic_unsupported = true;
190 }
191
192 if (stat_regB.dm) {
193 inform("RTC: The binary interface is not fully implemented.\n");
194 panic_unsupported = true;
195 }
196
197 if (!stat_regB.format24h) {
198 inform("RTC: The 12h time format not supported.\n");
199 panic_unsupported = true;
200 }
201
202 if (stat_regB.dse) {
203 inform("RTC: Automatic daylight saving time not supported.\n");
204 panic_unsupported = true;
205 }
206
207 if (stat_regB.pie) {
208 if (!event.scheduled())
209 event.scheduleIntr();
210 } else {
211 if (event.scheduled())
212 deschedule(event);
213 }
214 break;
215 case RTC_STAT_REGC:
216 case RTC_STAT_REGD:
217 panic("RTC status registers C and D are not implemented.\n");
218 break;
219 }
220 }
221
222 if (panic_unsupported)
223 panic("Unimplemented RTC configuration!\n");
224
225}
226
227uint8_t
228MC146818::readData(uint8_t addr)
229{
230 if (addr < RTC_STAT_REGA)
231 return clock_data[addr];
232 else {
233 switch (addr) {
234 case RTC_STAT_REGA:
235 // toggle UIP bit for linux
236 stat_regA.uip = !stat_regA.uip;
237 return stat_regA;
238 break;
239 case RTC_STAT_REGB:
240 return stat_regB;
241 break;
242 case RTC_STAT_REGC:
243 case RTC_STAT_REGD:
244 return 0x00;
245 break;
246 default:
247 panic("Shouldn't be here");
248 }
249 }
250}
251
252void
253MC146818::tickClock()
254{
255 assert(!rega_dv_disabled(stat_regA));
256
257 if (stat_regB.set)
258 return;
259 time_t calTime = mkutctime(&curTime);
260 calTime++;
261 setTime(*gmtime(&calTime));
262}
263
264void
265MC146818::serialize(const string &base, ostream &os)
266{
267 uint8_t regA_serial(stat_regA);
268 uint8_t regB_serial(stat_regB);
269
270 arrayParamOut(os, base + ".clock_data", clock_data, sizeof(clock_data));
271 paramOut(os, base + ".stat_regA", (uint8_t)regA_serial);
272 paramOut(os, base + ".stat_regB", (uint8_t)regB_serial);
273
274 //
275 // save the timer tick and rtc clock tick values to correctly reschedule
276 // them during unserialize
277 //
278 Tick rtcTimerInterruptTickOffset = event.when() - curTick();
279 SERIALIZE_SCALAR(rtcTimerInterruptTickOffset);
280 Tick rtcClockTickOffset = tickEvent.when() - curTick();
281 SERIALIZE_SCALAR(rtcClockTickOffset);
282}
283
284void
285MC146818::unserialize(const string &base, Checkpoint *cp,
286 const string §ion)
287{
288 uint8_t tmp8;
289
290 arrayParamIn(cp, section, base + ".clock_data", clock_data,
291 sizeof(clock_data));
292
293 paramIn(cp, section, base + ".stat_regA", tmp8);
294 stat_regA = tmp8;
295 paramIn(cp, section, base + ".stat_regB", tmp8);
296 stat_regB = tmp8;
297
298 //
299 // properly schedule the timer and rtc clock events
300 //
301 Tick rtcTimerInterruptTickOffset;
302 UNSERIALIZE_SCALAR(rtcTimerInterruptTickOffset);
303 event.offset = rtcTimerInterruptTickOffset;
304 Tick rtcClockTickOffset;
305 UNSERIALIZE_SCALAR(rtcClockTickOffset);
306 tickEvent.offset = rtcClockTickOffset;
307}
308
309MC146818::RTCEvent::RTCEvent(MC146818 * _parent, Tick i)
310 : parent(_parent), interval(i), offset(i)
311{
312 DPRINTF(MC146818, "RTC Event Initilizing\n");
313}
314
315void
316MC146818::RTCEvent::scheduleIntr()
317{
318 parent->schedule(this, curTick() + interval);
319}
320
321void
322MC146818::RTCEvent::process()
323{
324 DPRINTF(MC146818, "RTC Timer Interrupt\n");
325 parent->schedule(this, curTick() + interval);
326 parent->handleEvent();
327}
328
329const char *
330MC146818::RTCEvent::description() const
331{
332 return "RTC interrupt";
333}
334
335void
336MC146818::RTCTickEvent::process()
337{
338 DPRINTF(MC146818, "RTC clock tick\n");
339 parent->schedule(this, curTick() + SimClock::Int::s);
340 parent->tickClock();
341}
342
343const char *
344MC146818::RTCTickEvent::description() const
345{
346 return "RTC clock tick";
347}
| 135}
136
137void
138MC146818::writeData(const uint8_t addr, const uint8_t data)
139{
140 bool panic_unsupported(false);
141
142 if (addr < RTC_STAT_REGA) {
143 clock_data[addr] = data;
144 curTime.tm_sec = unbcdize(sec);
145 curTime.tm_min = unbcdize(min);
146 curTime.tm_hour = unbcdize(hour);
147 curTime.tm_mday = unbcdize(mday);
148 curTime.tm_mon = unbcdize(mon) - 1;
149 curTime.tm_year = ((unbcdize(year) + 50) % 100) + 1950;
150 curTime.tm_wday = unbcdize(wday) - 1;
151 } else {
152 switch (addr) {
153 case RTC_STAT_REGA: {
154 RtcRegA old_rega(stat_regA);
155 stat_regA = data;
156 // The "update in progress" bit is read only.
157 stat_regA.uip = old_rega;
158
159 if (!rega_dv_disabled(stat_regA) &&
160 stat_regA.dv != RTCA_DV_32768HZ) {
161 inform("RTC: Unimplemented divider configuration: %i\n",
162 stat_regA.dv);
163 panic_unsupported = true;
164 }
165
166 if (stat_regA.rs != RTCA_RS_1024HZ) {
167 inform("RTC: Unimplemented interrupt rate: %i\n",
168 stat_regA.rs);
169 panic_unsupported = true;
170 }
171
172 if (rega_dv_disabled(stat_regA)) {
173 // The divider is disabled, make sure that we don't
174 // schedule any ticks.
175 if (tickEvent.scheduled())
176 deschedule(tickEvent);
177 } else if (rega_dv_disabled(old_rega)) {
178 // According to the specification, the next tick
179 // happens after 0.5s when the divider chain goes
180 // from reset to active. So, we simply schedule the
181 // tick after 0.5s.
182 assert(!tickEvent.scheduled());
183 schedule(tickEvent, curTick() + SimClock::Int::s / 2);
184 }
185 } break;
186 case RTC_STAT_REGB:
187 stat_regB = data;
188 if (stat_regB.aie || stat_regB.uie) {
189 inform("RTC: Unimplemented interrupt configuration: %s %s\n",
190 stat_regB.aie ? "alarm" : "",
191 stat_regB.uie ? "update" : "");
192 panic_unsupported = true;
193 }
194
195 if (stat_regB.dm) {
196 inform("RTC: The binary interface is not fully implemented.\n");
197 panic_unsupported = true;
198 }
199
200 if (!stat_regB.format24h) {
201 inform("RTC: The 12h time format not supported.\n");
202 panic_unsupported = true;
203 }
204
205 if (stat_regB.dse) {
206 inform("RTC: Automatic daylight saving time not supported.\n");
207 panic_unsupported = true;
208 }
209
210 if (stat_regB.pie) {
211 if (!event.scheduled())
212 event.scheduleIntr();
213 } else {
214 if (event.scheduled())
215 deschedule(event);
216 }
217 break;
218 case RTC_STAT_REGC:
219 case RTC_STAT_REGD:
220 panic("RTC status registers C and D are not implemented.\n");
221 break;
222 }
223 }
224
225 if (panic_unsupported)
226 panic("Unimplemented RTC configuration!\n");
227
228}
229
230uint8_t
231MC146818::readData(uint8_t addr)
232{
233 if (addr < RTC_STAT_REGA)
234 return clock_data[addr];
235 else {
236 switch (addr) {
237 case RTC_STAT_REGA:
238 // toggle UIP bit for linux
239 stat_regA.uip = !stat_regA.uip;
240 return stat_regA;
241 break;
242 case RTC_STAT_REGB:
243 return stat_regB;
244 break;
245 case RTC_STAT_REGC:
246 case RTC_STAT_REGD:
247 return 0x00;
248 break;
249 default:
250 panic("Shouldn't be here");
251 }
252 }
253}
254
255void
256MC146818::tickClock()
257{
258 assert(!rega_dv_disabled(stat_regA));
259
260 if (stat_regB.set)
261 return;
262 time_t calTime = mkutctime(&curTime);
263 calTime++;
264 setTime(*gmtime(&calTime));
265}
266
267void
268MC146818::serialize(const string &base, ostream &os)
269{
270 uint8_t regA_serial(stat_regA);
271 uint8_t regB_serial(stat_regB);
272
273 arrayParamOut(os, base + ".clock_data", clock_data, sizeof(clock_data));
274 paramOut(os, base + ".stat_regA", (uint8_t)regA_serial);
275 paramOut(os, base + ".stat_regB", (uint8_t)regB_serial);
276
277 //
278 // save the timer tick and rtc clock tick values to correctly reschedule
279 // them during unserialize
280 //
281 Tick rtcTimerInterruptTickOffset = event.when() - curTick();
282 SERIALIZE_SCALAR(rtcTimerInterruptTickOffset);
283 Tick rtcClockTickOffset = tickEvent.when() - curTick();
284 SERIALIZE_SCALAR(rtcClockTickOffset);
285}
286
287void
288MC146818::unserialize(const string &base, Checkpoint *cp,
289 const string §ion)
290{
291 uint8_t tmp8;
292
293 arrayParamIn(cp, section, base + ".clock_data", clock_data,
294 sizeof(clock_data));
295
296 paramIn(cp, section, base + ".stat_regA", tmp8);
297 stat_regA = tmp8;
298 paramIn(cp, section, base + ".stat_regB", tmp8);
299 stat_regB = tmp8;
300
301 //
302 // properly schedule the timer and rtc clock events
303 //
304 Tick rtcTimerInterruptTickOffset;
305 UNSERIALIZE_SCALAR(rtcTimerInterruptTickOffset);
306 event.offset = rtcTimerInterruptTickOffset;
307 Tick rtcClockTickOffset;
308 UNSERIALIZE_SCALAR(rtcClockTickOffset);
309 tickEvent.offset = rtcClockTickOffset;
310}
311
312MC146818::RTCEvent::RTCEvent(MC146818 * _parent, Tick i)
313 : parent(_parent), interval(i), offset(i)
314{
315 DPRINTF(MC146818, "RTC Event Initilizing\n");
316}
317
318void
319MC146818::RTCEvent::scheduleIntr()
320{
321 parent->schedule(this, curTick() + interval);
322}
323
324void
325MC146818::RTCEvent::process()
326{
327 DPRINTF(MC146818, "RTC Timer Interrupt\n");
328 parent->schedule(this, curTick() + interval);
329 parent->handleEvent();
330}
331
332const char *
333MC146818::RTCEvent::description() const
334{
335 return "RTC interrupt";
336}
337
338void
339MC146818::RTCTickEvent::process()
340{
341 DPRINTF(MC146818, "RTC clock tick\n");
342 parent->schedule(this, curTick() + SimClock::Int::s);
343 parent->tickClock();
344}
345
346const char *
347MC146818::RTCTickEvent::description() const
348{
349 return "RTC clock tick";
350}
|