1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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30 * Miguel Serrano
31 */
32
33#include <sys/time.h>
34#include <time.h>
35
36#include <string>
37
38#include "base/time.hh"
39#include "base/trace.hh"
40#include "dev/mc146818.hh"
41#include "dev/rtcreg.h"
42
43using namespace std;
44
45MC146818::MC146818(EventManager *em, const string &n, const struct tm time,

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82void
83MC146818::writeData(const uint8_t addr, const uint8_t data)
84{
85 if (addr < RTC_STAT_REGA)
86 clock_data[addr] = data;
87 else {
88 switch (addr) {
89 case RTC_STAT_REGA:
90 if (data != (RTCA_32768HZ | RTCA_1024HZ))
91 panic("Unimplemented RTC register A value write!\n");
92 stat_regA = data;
93 break;
94 case RTC_STAT_REGB:
95 if ((data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != (RTCB_BIN | RTCB_24HR))
96 panic("Write to RTC reg B bits that are not implemented!\n");
97
98 if (data & RTCB_PRDC_IE) {
99 if (!event.scheduled())
100 event.scheduleIntr();

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