1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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30 * Miguel Serrano
31 */
32
33#include <sys/time.h>
34#include <time.h>
35
36#include <string>
37
38#include "base/bitfield.hh"
39#include "base/time.hh"
40#include "base/trace.hh"
41#include "dev/mc146818.hh"
42#include "dev/rtcreg.h"
43
44using namespace std;
45
46MC146818::MC146818(EventManager *em, const string &n, const struct tm time,

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83void
84MC146818::writeData(const uint8_t addr, const uint8_t data)
85{
86 if (addr < RTC_STAT_REGA)
87 clock_data[addr] = data;
88 else {
89 switch (addr) {
90 case RTC_STAT_REGA:
91 // The "update in progress" bit is read only.
92 if ((data & ~RTCA_UIP) != (RTCA_32768HZ | RTCA_1024HZ))
93 panic("Unimplemented RTC register A value write!\n");
94 replaceBits(stat_regA, data, 6, 0);
95 break;
96 case RTC_STAT_REGB:
97 if ((data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != (RTCB_BIN | RTCB_24HR))
98 panic("Write to RTC reg B bits that are not implemented!\n");
99
100 if (data & RTCB_PRDC_IE) {
101 if (!event.scheduled())
102 event.scheduleIntr();

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