io_device.hh (4965:ad0e792a5c78) | io_device.hh (5386:5614618f4027) |
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1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27 * 28 * Authors: Ali Saidi 29 * Nathan Binkert 30 */ 31 32#ifndef __DEV_IO_DEVICE_HH__ 33#define __DEV_IO_DEVICE_HH__ 34 | 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27 * 28 * Authors: Ali Saidi 29 * Nathan Binkert 30 */ 31 32#ifndef __DEV_IO_DEVICE_HH__ 33#define __DEV_IO_DEVICE_HH__ 34 |
35#include "base/fast_alloc.hh" |
|
35#include "mem/mem_object.hh" 36#include "mem/packet.hh" 37#include "mem/tport.hh" 38#include "params/BasicPioDevice.hh" 39#include "params/DmaDevice.hh" 40#include "params/PioDevice.hh" 41#include "sim/sim_object.hh" 42 --- 25 unchanged lines hidden (view full) --- 68 69 PioPort(PioDevice *dev, System *s, std::string pname = "-pioport"); 70}; 71 72 73class DmaPort : public Port 74{ 75 protected: | 36#include "mem/mem_object.hh" 37#include "mem/packet.hh" 38#include "mem/tport.hh" 39#include "params/BasicPioDevice.hh" 40#include "params/DmaDevice.hh" 41#include "params/PioDevice.hh" 42#include "sim/sim_object.hh" 43 --- 25 unchanged lines hidden (view full) --- 69 70 PioPort(PioDevice *dev, System *s, std::string pname = "-pioport"); 71}; 72 73 74class DmaPort : public Port 75{ 76 protected: |
76 struct DmaReqState : public Packet::SenderState | 77 struct DmaReqState : public Packet::SenderState, public FastAlloc |
77 { 78 /** Event to call on the device when this transaction (all packets) 79 * complete. */ 80 Event *completionEvent; 81 82 /** Where we came from for some sanity checking. */ 83 Port *outPort; 84 --- 219 unchanged lines hidden --- | 78 { 79 /** Event to call on the device when this transaction (all packets) 80 * complete. */ 81 Event *completionEvent; 82 83 /** Where we came from for some sanity checking. */ 84 Port *outPort; 85 --- 219 unchanged lines hidden --- |