1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 75 unchanged lines hidden (view full) --- 84 Port *outPort; 85 86 /** Total number of bytes that this transaction involves. */ 87 Addr totBytes; 88 89 /** Number of bytes that have been acked for this transaction. */ 90 Addr numBytes; 91 |
92 /** Amount to delay completion of dma by */ 93 Tick delay; 94 95 DmaReqState(Event *ce, Port *p, Addr tb, Tick _delay) 96 : completionEvent(ce), outPort(p), totBytes(tb), numBytes(0), 97 delay(_delay) |
98 {} 99 }; 100 101 DmaDevice *device; 102 std::list<PacketPtr> transmitList; 103 104 /** The system that device/port are in. This is used to select which mode 105 * we are currently operating in. */ --- 37 unchanged lines hidden (view full) --- 143 144 /** event to give us a kick every time we backoff time is reached. */ 145 EventWrapper<DmaPort, &DmaPort::sendDma> backoffEvent; 146 147 public: 148 DmaPort(DmaDevice *dev, System *s); 149 150 void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, |
151 uint8_t *data, Tick delay); |
152 153 bool dmaPending() { return pendingCount > 0; } 154 155 int cacheBlockSize() { return peerBlockSize(); } 156 unsigned int drain(Event *de); 157}; 158 159/** --- 104 unchanged lines hidden (view full) --- 264 virtual ~DmaDevice(); 265 266 const Params * 267 params() const 268 { 269 return dynamic_cast<const Params *>(_params); 270 } 271 |
272 void dmaWrite(Addr addr, int size, Event *event, uint8_t *data, Tick delay = 0) |
273 { |
274 dmaPort->dmaAction(MemCmd::WriteReq, addr, size, event, data, delay); |
275 } 276 |
277 void dmaRead(Addr addr, int size, Event *event, uint8_t *data, Tick delay = 0) |
278 { |
279 dmaPort->dmaAction(MemCmd::ReadReq, addr, size, event, data, delay); |
280 } 281 282 bool dmaPending() { return dmaPort->dmaPending(); } 283 284 virtual unsigned int drain(Event *de); 285 286 int cacheBlockSize() { return dmaPort->cacheBlockSize(); } 287 --- 21 unchanged lines hidden --- |