io_device.cc (4437:b6e304245729) io_device.cc (4451:bfb7c7c0b7ea)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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213 uint8_t *data)
214{
215 assert(event);
216
217 assert(device->getState() == SimObject::Running);
218
219 DmaReqState *reqState = new DmaReqState(event, this, size);
220
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 204 unchanged lines hidden (view full) ---

213 uint8_t *data)
214{
215 assert(event);
216
217 assert(device->getState() == SimObject::Running);
218
219 DmaReqState *reqState = new DmaReqState(event, this, size);
220
221
222 DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size,
223 event->scheduled());
221 for (ChunkGenerator gen(addr, size, peerBlockSize());
222 !gen.done(); gen.next()) {
223 Request *req = new Request(gen.addr(), gen.size(), 0);
224 PacketPtr pkt = new Packet(req, cmd, Packet::Broadcast);
225
226 // Increment the data pointer on a write
227 if (data)
228 pkt->dataStatic(data + gen.complete());
229
230 pkt->senderState = reqState;
231
232 assert(pendingCount >= 0);
233 pendingCount++;
224 for (ChunkGenerator gen(addr, size, peerBlockSize());
225 !gen.done(); gen.next()) {
226 Request *req = new Request(gen.addr(), gen.size(), 0);
227 PacketPtr pkt = new Packet(req, cmd, Packet::Broadcast);
228
229 // Increment the data pointer on a write
230 if (data)
231 pkt->dataStatic(data + gen.complete());
232
233 pkt->senderState = reqState;
234
235 assert(pendingCount >= 0);
236 pendingCount++;
237 DPRINTF(DMA, "--Queuing DMA for addr: %#x size: %d\n", gen.addr(),
238 gen.size());
234 queueDma(pkt);
235 }
236
237}
238
239void
240DmaPort::queueDma(PacketPtr pkt, bool front)
241{

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276 } else {
277 inRetry = true;
278 DPRINTF(DMA, "-- Failed: queued\n");
279 }
280 } while (result && !backoffTime && transmitList.size());
281
282 if (transmitList.size() && backoffTime && !inRetry &&
283 !backoffEvent.scheduled()) {
239 queueDma(pkt);
240 }
241
242}
243
244void
245DmaPort::queueDma(PacketPtr pkt, bool front)
246{

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281 } else {
282 inRetry = true;
283 DPRINTF(DMA, "-- Failed: queued\n");
284 }
285 } while (result && !backoffTime && transmitList.size());
286
287 if (transmitList.size() && backoffTime && !inRetry &&
288 !backoffEvent.scheduled()) {
289 DPRINTF(DMA, "-- Scheduling backoff timer for %d\n",
290 backoffTime+curTick);
284 backoffEvent.schedule(backoffTime+curTick);
285 }
286 } else if (state == System::Atomic) {
287 transmitList.pop_front();
288
289 Tick lat;
291 backoffEvent.schedule(backoffTime+curTick);
292 }
293 } else if (state == System::Atomic) {
294 transmitList.pop_front();
295
296 Tick lat;
297 DPRINTF(DMA, "--Sending DMA for addr: %#x size: %d\n",
298 pkt->req->getPaddr(), pkt->req->getSize());
290 lat = sendAtomic(pkt);
291 assert(pkt->senderState);
292 DmaReqState *state = dynamic_cast<DmaReqState*>(pkt->senderState);
293 assert(state);
299 lat = sendAtomic(pkt);
300 assert(pkt->senderState);
301 DmaReqState *state = dynamic_cast<DmaReqState*>(pkt->senderState);
302 assert(state);
294
295 state->numBytes += pkt->req->getSize();
303 state->numBytes += pkt->req->getSize();
304
305 DPRINTF(DMA, "--Received response for DMA for addr: %#x size: %d nb: %d, tot: %d sched %d\n",
306 pkt->req->getPaddr(), pkt->req->getSize(), state->numBytes,
307 state->totBytes, state->completionEvent->scheduled());
308
296 if (state->totBytes == state->numBytes) {
309 if (state->totBytes == state->numBytes) {
310 assert(!state->completionEvent->scheduled());
297 state->completionEvent->schedule(curTick + lat);
298 delete state;
299 delete pkt->req;
300 }
301 pendingCount--;
302 assert(pendingCount >= 0);
303 delete pkt;
304

--- 16 unchanged lines hidden --- 		311 state->completionEvent->schedule(curTick + lat);
312 delete state;
313 delete pkt->req;
314 }
315 pendingCount--;
316 assert(pendingCount >= 0);
317 delete pkt;
318

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