intel_8254_timer.cc (10905:a6ca6831e775) intel_8254_timer.cc (11321:02e930db812d)
1/*
2 * Copyright (c) 2004, 2005
3 * The Regents of The University of Michigan
4 * All Rights Reserved
5 *
6 * This code is part of the M5 simulator.
7 *
8 * Permission is granted to use, copy, create derivative works and

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105{
106 offset = period * event.getInterval();
107}
108
109void
110Intel8254Timer::Counter::latchCount()
111{
112 // behave like a real latch
1/*
2 * Copyright (c) 2004, 2005
3 * The Regents of The University of Michigan
4 * All Rights Reserved
5 *
6 * This code is part of the M5 simulator.
7 *
8 * Permission is granted to use, copy, create derivative works and

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105{
106 offset = period * event.getInterval();
107}
108
109void
110Intel8254Timer::Counter::latchCount()
111{
112 // behave like a real latch
113 if(!latch_on) {
113 if (!latch_on) {
114 latch_on = true;
115 read_byte = LSB;
116 latched_count = currentCount();
117 }
118}
119
120int
121Intel8254Timer::Counter::currentCount()

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202{
203 if (rw_val != TwoPhase)
204 panic("Only LSB/MSB read/write is implemented.\n");
205}
206
207void
208Intel8254Timer::Counter::setMode(int mode_val)
209{
114 latch_on = true;
115 read_byte = LSB;
116 latched_count = currentCount();
117 }
118}
119
120int
121Intel8254Timer::Counter::currentCount()

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202{
203 if (rw_val != TwoPhase)
204 panic("Only LSB/MSB read/write is implemented.\n");
205}
206
207void
208Intel8254Timer::Counter::setMode(int mode_val)
209{
210 if(mode_val != InitTc && mode_val != RateGen &&
210 if (mode_val != InitTc && mode_val != RateGen &&
211 mode_val != SquareWave)
212 panic("PIT mode %#x is not implemented: \n", mode_val);
213
214 mode = mode_val;
215}
216
217void
218Intel8254Timer::Counter::setBCD(int bcd_val)

--- 110 unchanged lines hidden --- 		211 mode_val != SquareWave)
212 panic("PIT mode %#x is not implemented: \n", mode_val);
213
214 mode = mode_val;
215}
216
217void
218Intel8254Timer::Counter::setBCD(int bcd_val)

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