1/* 2 * Copyright (c) 2004, 2005 3 * The Regents of The University of Michigan 4 * All Rights Reserved 5 * 6 * This code is part of the M5 simulator. 7 * 8 * Permission is granted to use, copy, create derivative works and 9 * redistribute this software and such derivative works for any 10 * purpose, so long as the copyright notice above, this grant of 11 * permission, and the disclaimer below appear in all copies made; and 12 * so long as the name of The University of Michigan is not used in 13 * any advertising or publicity pertaining to the use or distribution 14 * of this software without specific, written prior authorization. 15 * 16 * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE 17 * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND 18 * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER 19 * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE 22 * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT, 23 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM 24 * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN 25 * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH 26 * DAMAGES. 27 * 28 * Authors: Ali G. Saidi 29 * Andrew L. Schultz 30 * Miguel J. Serrano 31 */ 32 33#include "base/misc.hh" 34#include "dev/intel_8254_timer.hh" 35 36using namespace std; 37 38Intel8254Timer::Intel8254Timer(EventManager *em, const string &name, 39 Counter *counter0, Counter *counter1, Counter *counter2) : 40 EventManager(em), _name(name) 41{ 42 counter[0] = counter0; 43 counter[1] = counter1; 44 counter[2] = counter2; 45} 46 47Intel8254Timer::Intel8254Timer(EventManager *em, const string &name) : 48 EventManager(em), _name(name) 49{ 50 counter[0] = new Counter(this, name + ".counter0", 0); 51 counter[1] = new Counter(this, name + ".counter1", 1); 52 counter[2] = new Counter(this, name + ".counter2", 2); 53} 54 55void 56Intel8254Timer::writeControl(const CtrlReg data) 57{ 58 int sel = data.sel; 59 60 if (sel == ReadBackCommand) 61 panic("PITimer Read-Back Command is not implemented.\n"); 62 63 if (data.rw == LatchCommand) 64 counter[sel]->latchCount(); 65 else { 66 counter[sel]->setRW(data.rw); 67 counter[sel]->setMode(data.mode); 68 counter[sel]->setBCD(data.bcd); 69 } 70} 71 72void 73Intel8254Timer::serialize(const string &base, ostream &os) 74{ 75 // serialize the counters 76 counter[0]->serialize(base + ".counter0", os); 77 counter[1]->serialize(base + ".counter1", os); 78 counter[2]->serialize(base + ".counter2", os); 79} 80 81void 82Intel8254Timer::unserialize(const string &base, Checkpoint *cp, 83 const string §ion) 84{ 85 // unserialze the counters 86 counter[0]->unserialize(base + ".counter0", cp, section); 87 counter[1]->unserialize(base + ".counter1", cp, section); 88 counter[2]->unserialize(base + ".counter2", cp, section); 89} 90 91Intel8254Timer::Counter::Counter(Intel8254Timer *p, 92 const string &name, unsigned int _num)
| 1/* 2 * Copyright (c) 2004, 2005 3 * The Regents of The University of Michigan 4 * All Rights Reserved 5 * 6 * This code is part of the M5 simulator. 7 * 8 * Permission is granted to use, copy, create derivative works and 9 * redistribute this software and such derivative works for any 10 * purpose, so long as the copyright notice above, this grant of 11 * permission, and the disclaimer below appear in all copies made; and 12 * so long as the name of The University of Michigan is not used in 13 * any advertising or publicity pertaining to the use or distribution 14 * of this software without specific, written prior authorization. 15 * 16 * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE 17 * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND 18 * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER 19 * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE 22 * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT, 23 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM 24 * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN 25 * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH 26 * DAMAGES. 27 * 28 * Authors: Ali G. Saidi 29 * Andrew L. Schultz 30 * Miguel J. Serrano 31 */ 32 33#include "base/misc.hh" 34#include "dev/intel_8254_timer.hh" 35 36using namespace std; 37 38Intel8254Timer::Intel8254Timer(EventManager *em, const string &name, 39 Counter *counter0, Counter *counter1, Counter *counter2) : 40 EventManager(em), _name(name) 41{ 42 counter[0] = counter0; 43 counter[1] = counter1; 44 counter[2] = counter2; 45} 46 47Intel8254Timer::Intel8254Timer(EventManager *em, const string &name) : 48 EventManager(em), _name(name) 49{ 50 counter[0] = new Counter(this, name + ".counter0", 0); 51 counter[1] = new Counter(this, name + ".counter1", 1); 52 counter[2] = new Counter(this, name + ".counter2", 2); 53} 54 55void 56Intel8254Timer::writeControl(const CtrlReg data) 57{ 58 int sel = data.sel; 59 60 if (sel == ReadBackCommand) 61 panic("PITimer Read-Back Command is not implemented.\n"); 62 63 if (data.rw == LatchCommand) 64 counter[sel]->latchCount(); 65 else { 66 counter[sel]->setRW(data.rw); 67 counter[sel]->setMode(data.mode); 68 counter[sel]->setBCD(data.bcd); 69 } 70} 71 72void 73Intel8254Timer::serialize(const string &base, ostream &os) 74{ 75 // serialize the counters 76 counter[0]->serialize(base + ".counter0", os); 77 counter[1]->serialize(base + ".counter1", os); 78 counter[2]->serialize(base + ".counter2", os); 79} 80 81void 82Intel8254Timer::unserialize(const string &base, Checkpoint *cp, 83 const string §ion) 84{ 85 // unserialze the counters 86 counter[0]->unserialize(base + ".counter0", cp, section); 87 counter[1]->unserialize(base + ".counter1", cp, section); 88 counter[2]->unserialize(base + ".counter2", cp, section); 89} 90 91Intel8254Timer::Counter::Counter(Intel8254Timer *p, 92 const string &name, unsigned int _num)
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93 : _name(name), num(_num), event(this), count(0),
| 93 : _name(name), num(_num), event(this), initial_count(0),
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94 latched_count(0), period(0), mode(0), output_high(false), 95 latch_on(false), read_byte(LSB), write_byte(LSB), parent(p) 96{ 97 98} 99 100void 101Intel8254Timer::Counter::latchCount() 102{ 103 // behave like a real latch 104 if(!latch_on) { 105 latch_on = true; 106 read_byte = LSB;
| 94 latched_count(0), period(0), mode(0), output_high(false), 95 latch_on(false), read_byte(LSB), write_byte(LSB), parent(p) 96{ 97 98} 99 100void 101Intel8254Timer::Counter::latchCount() 102{ 103 // behave like a real latch 104 if(!latch_on) { 105 latch_on = true; 106 read_byte = LSB;
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107 latched_count = count;
| 107 latched_count = currentCount();
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108 } 109} 110
| 108 } 109} 110
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| 111int 112Intel8254Timer::Counter::currentCount() 113{ 114 int clocks = event.clocksLeft(); 115 if (clocks == -1) { 116 warn_once("Reading current count from inactive timer.\n"); 117 return 0; 118 } 119 if (mode == RateGen || mode == SquareWave) 120 return clocks + 1; 121 else 122 return clocks; 123} 124
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111uint8_t 112Intel8254Timer::Counter::read() 113{ 114 if (latch_on) { 115 switch (read_byte) { 116 case LSB: 117 read_byte = MSB; 118 return (uint8_t)latched_count; 119 break; 120 case MSB: 121 read_byte = LSB; 122 latch_on = false; 123 return latched_count >> 8; 124 break; 125 default: 126 panic("Shouldn't be here"); 127 } 128 } else {
| 125uint8_t 126Intel8254Timer::Counter::read() 127{ 128 if (latch_on) { 129 switch (read_byte) { 130 case LSB: 131 read_byte = MSB; 132 return (uint8_t)latched_count; 133 break; 134 case MSB: 135 read_byte = LSB; 136 latch_on = false; 137 return latched_count >> 8; 138 break; 139 default: 140 panic("Shouldn't be here"); 141 } 142 } else {
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| 143 uint16_t count = currentCount();
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129 switch (read_byte) { 130 case LSB: 131 read_byte = MSB; 132 return (uint8_t)count; 133 break; 134 case MSB: 135 read_byte = LSB; 136 return count >> 8; 137 break; 138 default: 139 panic("Shouldn't be here"); 140 } 141 } 142} 143 144void 145Intel8254Timer::Counter::write(const uint8_t data) 146{ 147 switch (write_byte) { 148 case LSB:
| 144 switch (read_byte) { 145 case LSB: 146 read_byte = MSB; 147 return (uint8_t)count; 148 break; 149 case MSB: 150 read_byte = LSB; 151 return count >> 8; 152 break; 153 default: 154 panic("Shouldn't be here"); 155 } 156 } 157} 158 159void 160Intel8254Timer::Counter::write(const uint8_t data) 161{ 162 switch (write_byte) { 163 case LSB:
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149 count = (count & 0xFF00) | data;
| 164 initial_count = (initial_count & 0xFF00) | data;
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150 151 if (event.scheduled()) 152 parent->deschedule(event); 153 output_high = false; 154 write_byte = MSB; 155 break; 156 157 case MSB:
| 165 166 if (event.scheduled()) 167 parent->deschedule(event); 168 output_high = false; 169 write_byte = MSB; 170 break; 171 172 case MSB:
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158 count = (count & 0x00FF) | (data << 8);
| 173 initial_count = (initial_count & 0x00FF) | (data << 8);
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159 // In the RateGen or SquareWave modes, the timer wraps around and 160 // triggers on a value of 1, not 0. 161 if (mode == RateGen || mode == SquareWave)
| 174 // In the RateGen or SquareWave modes, the timer wraps around and 175 // triggers on a value of 1, not 0. 176 if (mode == RateGen || mode == SquareWave)
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162 period = count - 1;
| 177 period = initial_count - 1;
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163 else
| 178 else
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164 period = count;
| 179 period = initial_count;
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165 166 if (period > 0) 167 event.setTo(period); 168 169 write_byte = LSB; 170 break; 171 } 172} 173 174void 175Intel8254Timer::Counter::setRW(int rw_val) 176{ 177 if (rw_val != TwoPhase) 178 panic("Only LSB/MSB read/write is implemented.\n"); 179} 180 181void 182Intel8254Timer::Counter::setMode(int mode_val) 183{ 184 if(mode_val != InitTc && mode_val != RateGen && 185 mode_val != SquareWave) 186 panic("PIT mode %#x is not implemented: \n", mode_val); 187 188 mode = mode_val; 189} 190 191void 192Intel8254Timer::Counter::setBCD(int bcd_val) 193{ 194 if (bcd_val) 195 panic("PITimer does not implement BCD counts.\n"); 196} 197 198bool 199Intel8254Timer::Counter::outputHigh() 200{ 201 return output_high; 202} 203 204void 205Intel8254Timer::Counter::serialize(const string &base, ostream &os) 206{
| 180 181 if (period > 0) 182 event.setTo(period); 183 184 write_byte = LSB; 185 break; 186 } 187} 188 189void 190Intel8254Timer::Counter::setRW(int rw_val) 191{ 192 if (rw_val != TwoPhase) 193 panic("Only LSB/MSB read/write is implemented.\n"); 194} 195 196void 197Intel8254Timer::Counter::setMode(int mode_val) 198{ 199 if(mode_val != InitTc && mode_val != RateGen && 200 mode_val != SquareWave) 201 panic("PIT mode %#x is not implemented: \n", mode_val); 202 203 mode = mode_val; 204} 205 206void 207Intel8254Timer::Counter::setBCD(int bcd_val) 208{ 209 if (bcd_val) 210 panic("PITimer does not implement BCD counts.\n"); 211} 212 213bool 214Intel8254Timer::Counter::outputHigh() 215{ 216 return output_high; 217} 218 219void 220Intel8254Timer::Counter::serialize(const string &base, ostream &os) 221{
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207 paramOut(os, base + ".count", count);
| 222 paramOut(os, base + ".initial_count", initial_count);
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208 paramOut(os, base + ".latched_count", latched_count); 209 paramOut(os, base + ".period", period); 210 paramOut(os, base + ".mode", mode); 211 paramOut(os, base + ".output_high", output_high); 212 paramOut(os, base + ".latch_on", latch_on); 213 paramOut(os, base + ".read_byte", read_byte); 214 paramOut(os, base + ".write_byte", write_byte); 215 216 Tick event_tick = 0; 217 if (event.scheduled()) 218 event_tick = event.when(); 219 paramOut(os, base + ".event_tick", event_tick); 220} 221 222void 223Intel8254Timer::Counter::unserialize(const string &base, Checkpoint *cp, 224 const string §ion) 225{
| 223 paramOut(os, base + ".latched_count", latched_count); 224 paramOut(os, base + ".period", period); 225 paramOut(os, base + ".mode", mode); 226 paramOut(os, base + ".output_high", output_high); 227 paramOut(os, base + ".latch_on", latch_on); 228 paramOut(os, base + ".read_byte", read_byte); 229 paramOut(os, base + ".write_byte", write_byte); 230 231 Tick event_tick = 0; 232 if (event.scheduled()) 233 event_tick = event.when(); 234 paramOut(os, base + ".event_tick", event_tick); 235} 236 237void 238Intel8254Timer::Counter::unserialize(const string &base, Checkpoint *cp, 239 const string §ion) 240{
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226 paramIn(cp, section, base + ".count", count);
| 241 paramIn(cp, section, base + ".initial_count", initial_count);
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227 paramIn(cp, section, base + ".latched_count", latched_count); 228 paramIn(cp, section, base + ".period", period); 229 paramIn(cp, section, base + ".mode", mode); 230 paramIn(cp, section, base + ".output_high", output_high); 231 paramIn(cp, section, base + ".latch_on", latch_on); 232 paramIn(cp, section, base + ".read_byte", read_byte); 233 paramIn(cp, section, base + ".write_byte", write_byte); 234 235 Tick event_tick; 236 paramIn(cp, section, base + ".event_tick", event_tick); 237 if (event_tick) 238 parent->schedule(event, event_tick); 239} 240 241Intel8254Timer::Counter::CounterEvent::CounterEvent(Counter* c_ptr) 242{ 243 interval = (Tick)(Clock::Float::s / 1193180.0); 244 counter = c_ptr; 245} 246 247void 248Intel8254Timer::Counter::CounterEvent::process() 249{ 250 switch (counter->mode) { 251 case InitTc: 252 counter->output_high = true; 253 break; 254 case RateGen: 255 case SquareWave: 256 setTo(counter->period); 257 break; 258 default: 259 panic("Unimplemented PITimer mode.\n"); 260 } 261 counter->parent->counterInterrupt(counter->num); 262} 263 264void 265Intel8254Timer::Counter::CounterEvent::setTo(int clocks) 266{ 267 if (clocks == 0) 268 panic("Timer can't be set to go off instantly.\n"); 269 DPRINTF(Intel8254Timer, "Timer set to curTick + %d\n", 270 clocks * interval); 271 counter->parent->schedule(this, curTick + clocks * interval); 272} 273
| 242 paramIn(cp, section, base + ".latched_count", latched_count); 243 paramIn(cp, section, base + ".period", period); 244 paramIn(cp, section, base + ".mode", mode); 245 paramIn(cp, section, base + ".output_high", output_high); 246 paramIn(cp, section, base + ".latch_on", latch_on); 247 paramIn(cp, section, base + ".read_byte", read_byte); 248 paramIn(cp, section, base + ".write_byte", write_byte); 249 250 Tick event_tick; 251 paramIn(cp, section, base + ".event_tick", event_tick); 252 if (event_tick) 253 parent->schedule(event, event_tick); 254} 255 256Intel8254Timer::Counter::CounterEvent::CounterEvent(Counter* c_ptr) 257{ 258 interval = (Tick)(Clock::Float::s / 1193180.0); 259 counter = c_ptr; 260} 261 262void 263Intel8254Timer::Counter::CounterEvent::process() 264{ 265 switch (counter->mode) { 266 case InitTc: 267 counter->output_high = true; 268 break; 269 case RateGen: 270 case SquareWave: 271 setTo(counter->period); 272 break; 273 default: 274 panic("Unimplemented PITimer mode.\n"); 275 } 276 counter->parent->counterInterrupt(counter->num); 277} 278 279void 280Intel8254Timer::Counter::CounterEvent::setTo(int clocks) 281{ 282 if (clocks == 0) 283 panic("Timer can't be set to go off instantly.\n"); 284 DPRINTF(Intel8254Timer, "Timer set to curTick + %d\n", 285 clocks * interval); 286 counter->parent->schedule(this, curTick + clocks * interval); 287} 288
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| 289int 290Intel8254Timer::Counter::CounterEvent::clocksLeft() 291{ 292 if (!scheduled()) 293 return -1; 294 return (when() - curTick + interval - 1) / interval; 295} 296
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274const char * 275Intel8254Timer::Counter::CounterEvent::description() const 276{ 277 return "Intel 8254 Interval timer"; 278}
| 297const char * 298Intel8254Timer::Counter::CounterEvent::description() const 299{ 300 return "Intel 8254 Interval timer"; 301}
|