dma_device.hh (9342:6fec8f26e56d) dma_device.hh (9814:7ad2b0186a32)
1/*
1/*
2 * Copyright (c) 2012 ARM Limited
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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44#ifndef __DEV_DMA_DEVICE_HH__
45#define __DEV_DMA_DEVICE_HH__
46
47#include <deque>
48
49#include "dev/io_device.hh"
50#include "params/DmaDevice.hh"
51#include "sim/drain.hh"
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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44#ifndef __DEV_DMA_DEVICE_HH__
45#define __DEV_DMA_DEVICE_HH__
46
47#include <deque>
48
49#include "dev/io_device.hh"
50#include "params/DmaDevice.hh"
51#include "sim/drain.hh"
52#include "sim/system.hh"
52
53class DmaPort : public MasterPort
54{
55 private:
56
57 /**
58 * Take the first packet of the transmit list and attempt to send
59 * it as a timing request. If it is successful, schedule the

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141
142 DmaPort(MemObject *dev, System *s);
143
144 void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
145 uint8_t *data, Tick delay, Request::Flags flag = 0);
146
147 bool dmaPending() const { return pendingCount > 0; }
148
53
54class DmaPort : public MasterPort
55{
56 private:
57
58 /**
59 * Take the first packet of the transmit list and attempt to send
60 * it as a timing request. If it is successful, schedule the

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142
143 DmaPort(MemObject *dev, System *s);
144
145 void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
146 uint8_t *data, Tick delay, Request::Flags flag = 0);
147
148 bool dmaPending() const { return pendingCount > 0; }
149
149 unsigned cacheBlockSize() const { return peerBlockSize(); }
150 unsigned int drain(DrainManager *drainManger);
151};
152
153class DmaDevice : public PioDevice
154{
155 protected:
156 DmaPort dmaPort;
157

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173 }
174
175 bool dmaPending() const { return dmaPort.dmaPending(); }
176
177 virtual void init();
178
179 unsigned int drain(DrainManager *drainManger);
180
150 unsigned int drain(DrainManager *drainManger);
151};
152
153class DmaDevice : public PioDevice
154{
155 protected:
156 DmaPort dmaPort;
157

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173 }
174
175 bool dmaPending() const { return dmaPort.dmaPending(); }
176
177 virtual void init();
178
179 unsigned int drain(DrainManager *drainManger);
180
181 unsigned cacheBlockSize() const { return dmaPort.cacheBlockSize(); }
181 unsigned int cacheBlockSize() const { return sys->cacheLineSize(); }
182
183 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
184 PortID idx = InvalidPortID);
185
186};
187
188#endif // __DEV_DMA_DEVICE_HH__
182
183 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
184 PortID idx = InvalidPortID);
185
186};
187
188#endif // __DEV_DMA_DEVICE_HH__