dma_device.hh (9307:98e05d58f9eb) | dma_device.hh (9342:6fec8f26e56d) |
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1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 34 unchanged lines hidden (view full) --- 43 44#ifndef __DEV_DMA_DEVICE_HH__ 45#define __DEV_DMA_DEVICE_HH__ 46 47#include <deque> 48 49#include "dev/io_device.hh" 50#include "params/DmaDevice.hh" | 1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 34 unchanged lines hidden (view full) --- 43 44#ifndef __DEV_DMA_DEVICE_HH__ 45#define __DEV_DMA_DEVICE_HH__ 46 47#include <deque> 48 49#include "dev/io_device.hh" 50#include "params/DmaDevice.hh" |
51#include "sim/drain.hh" |
|
51 52class DmaPort : public MasterPort 53{ 54 private: 55 56 /** 57 * Take the first packet of the transmit list and attempt to send 58 * it as a timing request. If it is successful, schedule the --- 59 unchanged lines hidden (view full) --- 118 /** Id for all requests */ 119 const MasterID masterId; 120 121 /** Number of outstanding packets the dma port has. */ 122 uint32_t pendingCount; 123 124 /** If we need to drain, keep the drain event around until we're done 125 * here.*/ | 52 53class DmaPort : public MasterPort 54{ 55 private: 56 57 /** 58 * Take the first packet of the transmit list and attempt to send 59 * it as a timing request. If it is successful, schedule the --- 59 unchanged lines hidden (view full) --- 119 /** Id for all requests */ 120 const MasterID masterId; 121 122 /** Number of outstanding packets the dma port has. */ 123 uint32_t pendingCount; 124 125 /** If we need to drain, keep the drain event around until we're done 126 * here.*/ |
126 Event *drainEvent; | 127 DrainManager *drainManager; |
127 128 /** If the port is currently waiting for a retry before it can 129 * send whatever it is that it's sending. */ 130 bool inRetry; 131 132 protected: 133 134 bool recvTimingResp(PacketPtr pkt); --- 6 unchanged lines hidden (view full) --- 141 DmaPort(MemObject *dev, System *s); 142 143 void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, 144 uint8_t *data, Tick delay, Request::Flags flag = 0); 145 146 bool dmaPending() const { return pendingCount > 0; } 147 148 unsigned cacheBlockSize() const { return peerBlockSize(); } | 128 129 /** If the port is currently waiting for a retry before it can 130 * send whatever it is that it's sending. */ 131 bool inRetry; 132 133 protected: 134 135 bool recvTimingResp(PacketPtr pkt); --- 6 unchanged lines hidden (view full) --- 142 DmaPort(MemObject *dev, System *s); 143 144 void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, 145 uint8_t *data, Tick delay, Request::Flags flag = 0); 146 147 bool dmaPending() const { return pendingCount > 0; } 148 149 unsigned cacheBlockSize() const { return peerBlockSize(); } |
149 unsigned int drain(Event *de); | 150 unsigned int drain(DrainManager *drainManger); |
150}; 151 152class DmaDevice : public PioDevice 153{ 154 protected: 155 DmaPort dmaPort; 156 157 public: --- 12 unchanged lines hidden (view full) --- 170 { 171 dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay); 172 } 173 174 bool dmaPending() const { return dmaPort.dmaPending(); } 175 176 virtual void init(); 177 | 151}; 152 153class DmaDevice : public PioDevice 154{ 155 protected: 156 DmaPort dmaPort; 157 158 public: --- 12 unchanged lines hidden (view full) --- 171 { 172 dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay); 173 } 174 175 bool dmaPending() const { return dmaPort.dmaPending(); } 176 177 virtual void init(); 178 |
178 virtual unsigned int drain(Event *de); | 179 unsigned int drain(DrainManager *drainManger); |
179 180 unsigned cacheBlockSize() const { return dmaPort.cacheBlockSize(); } 181 182 virtual BaseMasterPort &getMasterPort(const std::string &if_name, 183 PortID idx = InvalidPortID); 184 185}; 186 187#endif // __DEV_DMA_DEVICE_HH__ | 180 181 unsigned cacheBlockSize() const { return dmaPort.cacheBlockSize(); } 182 183 virtual BaseMasterPort &getMasterPort(const std::string &if_name, 184 PortID idx = InvalidPortID); 185 186}; 187 188#endif // __DEV_DMA_DEVICE_HH__ |