dma_device.hh (9294:8fb03b13de02) | dma_device.hh (9307:98e05d58f9eb) |
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1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 37 unchanged lines hidden (view full) --- 46 47#include <deque> 48 49#include "dev/io_device.hh" 50#include "params/DmaDevice.hh" 51 52class DmaPort : public MasterPort 53{ | 1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 37 unchanged lines hidden (view full) --- 46 47#include <deque> 48 49#include "dev/io_device.hh" 50#include "params/DmaDevice.hh" 51 52class DmaPort : public MasterPort 53{ |
54 protected: | 54 private: 55 56 /** 57 * Take the first packet of the transmit list and attempt to send 58 * it as a timing request. If it is successful, schedule the 59 * sending of the next packet, otherwise remember that we are 60 * waiting for a retry. 61 */ 62 void trySendTimingReq(); 63 64 /** 65 * For timing, attempt to send the first item on the transmit 66 * list, and if it is successful and there are more packets 67 * waiting, then schedule the sending of the next packet. For 68 * atomic, simply send and process everything on the transmit 69 * list. 70 */ 71 void sendDma(); 72 73 /** 74 * Handle a response packet by updating the corresponding DMA 75 * request state to reflect the bytes received, and also update 76 * the pending request counter. If the DMA request that this 77 * packet is part of is complete, then signal the completion event 78 * if present, potentially with a delay added to it. 79 * 80 * @param pkt Response packet to handler 81 * @param delay Additional delay for scheduling the completion event 82 */ 83 void handleResp(PacketPtr pkt, Tick delay = 0); 84 |
55 struct DmaReqState : public Packet::SenderState 56 { 57 /** Event to call on the device when this transaction (all packets) 58 * complete. */ 59 Event *completionEvent; 60 61 /** Total number of bytes that this transaction involves. */ | 85 struct DmaReqState : public Packet::SenderState 86 { 87 /** Event to call on the device when this transaction (all packets) 88 * complete. */ 89 Event *completionEvent; 90 91 /** Total number of bytes that this transaction involves. */ |
62 Addr totBytes; | 92 const Addr totBytes; |
63 64 /** Number of bytes that have been acked for this transaction. */ 65 Addr numBytes; 66 67 /** Amount to delay completion of dma by */ | 93 94 /** Number of bytes that have been acked for this transaction. */ 95 Addr numBytes; 96 97 /** Amount to delay completion of dma by */ |
68 Tick delay; | 98 const Tick delay; |
69 70 DmaReqState(Event *ce, Addr tb, Tick _delay) 71 : completionEvent(ce), totBytes(tb), numBytes(0), delay(_delay) 72 {} 73 }; 74 | 99 100 DmaReqState(Event *ce, Addr tb, Tick _delay) 101 : completionEvent(ce), totBytes(tb), numBytes(0), delay(_delay) 102 {} 103 }; 104 |
105 /** The device that owns this port. */ |
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75 MemObject *device; 76 | 106 MemObject *device; 107 |
77 /** Use a deque as we never to any insertion or removal in the middle */ | 108 /** Use a deque as we never do any insertion or removal in the middle */ |
78 std::deque<PacketPtr> transmitList; 79 | 109 std::deque<PacketPtr> transmitList; 110 |
111 /** Event used to schedule a future sending from the transmit list. */ 112 EventWrapper<DmaPort, &DmaPort::sendDma> sendEvent; 113 |
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80 /** The system that device/port are in. This is used to select which mode 81 * we are currently operating in. */ 82 System *sys; 83 84 /** Id for all requests */ | 114 /** The system that device/port are in. This is used to select which mode 115 * we are currently operating in. */ 116 System *sys; 117 118 /** Id for all requests */ |
85 MasterID masterId; | 119 const MasterID masterId; |
86 87 /** Number of outstanding packets the dma port has. */ 88 uint32_t pendingCount; 89 90 /** If we need to drain, keep the drain event around until we're done 91 * here.*/ 92 Event *drainEvent; 93 94 /** If the port is currently waiting for a retry before it can 95 * send whatever it is that it's sending. */ 96 bool inRetry; 97 | 120 121 /** Number of outstanding packets the dma port has. */ 122 uint32_t pendingCount; 123 124 /** If we need to drain, keep the drain event around until we're done 125 * here.*/ 126 Event *drainEvent; 127 128 /** If the port is currently waiting for a retry before it can 129 * send whatever it is that it's sending. */ 130 bool inRetry; 131 |
98 /** 99 * Handle a response packet by updating the corresponding DMA 100 * request state to reflect the bytes received, and also update 101 * the pending request counter. If the DMA request that this 102 * packet is part of is complete, then signal the completion event 103 * if present, potentially with a delay added to it. 104 * 105 * @param pkt Response packet to handler 106 * @param delay Additional delay for scheduling the completion event 107 */ 108 void handleResp(PacketPtr pkt, Tick delay = 0); | 132 protected: |
109 110 bool recvTimingResp(PacketPtr pkt); 111 void recvRetry() ; 112 113 void queueDma(PacketPtr pkt); | 133 134 bool recvTimingResp(PacketPtr pkt); 135 void recvRetry() ; 136 137 void queueDma(PacketPtr pkt); |
114 void sendDma(); | |
115 116 public: 117 118 DmaPort(MemObject *dev, System *s); 119 120 void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, 121 uint8_t *data, Tick delay, Request::Flags flag = 0); 122 --- 20 unchanged lines hidden (view full) --- 143 } 144 145 void dmaRead(Addr addr, int size, Event *event, uint8_t *data, 146 Tick delay = 0) 147 { 148 dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay); 149 } 150 | 138 139 public: 140 141 DmaPort(MemObject *dev, System *s); 142 143 void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, 144 uint8_t *data, Tick delay, Request::Flags flag = 0); 145 --- 20 unchanged lines hidden (view full) --- 166 } 167 168 void dmaRead(Addr addr, int size, Event *event, uint8_t *data, 169 Tick delay = 0) 170 { 171 dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay); 172 } 173 |
151 bool dmaPending() { return dmaPort.dmaPending(); } | 174 bool dmaPending() const { return dmaPort.dmaPending(); } |
152 153 virtual void init(); 154 155 virtual unsigned int drain(Event *de); 156 157 unsigned cacheBlockSize() const { return dmaPort.cacheBlockSize(); } 158 159 virtual BaseMasterPort &getMasterPort(const std::string &if_name, 160 PortID idx = InvalidPortID); 161 | 175 176 virtual void init(); 177 178 virtual unsigned int drain(Event *de); 179 180 unsigned cacheBlockSize() const { return dmaPort.cacheBlockSize(); } 181 182 virtual BaseMasterPort &getMasterPort(const std::string &if_name, 183 PortID idx = InvalidPortID); 184 |
162 friend class DmaPort; | |
163}; 164 165#endif // __DEV_DMA_DEVICE_HH__ | 185}; 186 187#endif // __DEV_DMA_DEVICE_HH__ |