dma_device.hh (9165:f9e3dac185ba) dma_device.hh (9166:1d983855df2c)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 30 unchanged lines hidden (view full) ---

39 *
40 * Authors: Ali Saidi
41 * Nathan Binkert
42 */
43
44#ifndef __DEV_DMA_DEVICE_HH__
45#define __DEV_DMA_DEVICE_HH__
46
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 30 unchanged lines hidden (view full) ---

39 *
40 * Authors: Ali Saidi
41 * Nathan Binkert
42 */
43
44#ifndef __DEV_DMA_DEVICE_HH__
45#define __DEV_DMA_DEVICE_HH__
46
47#include <deque>
48
47#include "dev/io_device.hh"
48#include "params/DmaDevice.hh"
49
50class DmaPort : public MasterPort
51{
52 protected:
53 struct DmaReqState : public Packet::SenderState
54 {

--- 11 unchanged lines hidden (view full) ---

66 Tick delay;
67
68 DmaReqState(Event *ce, Addr tb, Tick _delay)
69 : completionEvent(ce), totBytes(tb), numBytes(0), delay(_delay)
70 {}
71 };
72
73 MemObject *device;
49#include "dev/io_device.hh"
50#include "params/DmaDevice.hh"
51
52class DmaPort : public MasterPort
53{
54 protected:
55 struct DmaReqState : public Packet::SenderState
56 {

--- 11 unchanged lines hidden (view full) ---

68 Tick delay;
69
70 DmaReqState(Event *ce, Addr tb, Tick _delay)
71 : completionEvent(ce), totBytes(tb), numBytes(0), delay(_delay)
72 {}
73 };
74
75 MemObject *device;
74 std::list<PacketPtr> transmitList;
75
76
77 /** Use a deque as we never to any insertion or removal in the middle */
78 std::deque<PacketPtr> transmitList;
79
76 /** The system that device/port are in. This is used to select which mode
77 * we are currently operating in. */
78 System *sys;
79
80 /** Id for all requests */
81 MasterID masterId;
82
83 /** Number of outstanding packets the dma port has. */
80 /** The system that device/port are in. This is used to select which mode
81 * we are currently operating in. */
82 System *sys;
83
84 /** Id for all requests */
85 MasterID masterId;
86
87 /** Number of outstanding packets the dma port has. */
84 int pendingCount;
88 uint32_t pendingCount;
85
86 /** If we need to drain, keep the drain event around until we're done
87 * here.*/
88 Event *drainEvent;
89
89
90 /** If we need to drain, keep the drain event around until we're done
91 * here.*/
92 Event *drainEvent;
93
90 /** If the port is currently waiting for a retry before it can send whatever
91 * it is that it's sending. */
94 /** If the port is currently waiting for a retry before it can
95 * send whatever it is that it's sending. */
92 bool inRetry;
93
96 bool inRetry;
97
94 virtual bool recvTimingResp(PacketPtr pkt);
98 /**
99 * Handle a response packet by updating the corresponding DMA
100 * request state to reflect the bytes received, and also update
101 * the pending request counter. If the DMA request that this
102 * packet is part of is complete, then signal the completion event
103 * if present, potentially with a delay added to it.
104 *
105 * @param pkt Response packet to handler
106 * @param delay Additional delay for scheduling the completion event
107 */
108 void handleResp(PacketPtr pkt, Tick delay = 0);
95
109
96 virtual void recvRetry() ;
110 bool recvTimingResp(PacketPtr pkt);
111 void recvRetry() ;
97
112
98 void queueDma(PacketPtr pkt, bool front = false);
113 void queueDma(PacketPtr pkt);
99 void sendDma();
100
101 public:
102
103 DmaPort(MemObject *dev, System *s);
104
105 void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
106 uint8_t *data, Tick delay, Request::Flags flag = 0);
107
114 void sendDma();
115
116 public:
117
118 DmaPort(MemObject *dev, System *s);
119
120 void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
121 uint8_t *data, Tick delay, Request::Flags flag = 0);
122
108 bool dmaPending() { return pendingCount > 0; }
123 bool dmaPending() const { return pendingCount > 0; }
109
110 unsigned cacheBlockSize() const { return peerBlockSize(); }
111 unsigned int drain(Event *de);
112};
113
114class DmaDevice : public PioDevice
115{
116 protected:
117 DmaPort dmaPort;
118
119 public:
120 typedef DmaDeviceParams Params;
121 DmaDevice(const Params *p);
124
125 unsigned cacheBlockSize() const { return peerBlockSize(); }
126 unsigned int drain(Event *de);
127};
128
129class DmaDevice : public PioDevice
130{
131 protected:
132 DmaPort dmaPort;
133
134 public:
135 typedef DmaDeviceParams Params;
136 DmaDevice(const Params *p);
122 virtual ~DmaDevice();
137 virtual ~DmaDevice() { }
123
138
124 const Params *
125 params() const
126 {
127 return dynamic_cast<const Params *>(_params);
128 }
129
130 void dmaWrite(Addr addr, int size, Event *event, uint8_t *data,
131 Tick delay = 0)
132 {
133 dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data, delay);
134 }
135
136 void dmaRead(Addr addr, int size, Event *event, uint8_t *data,
137 Tick delay = 0)

--- 19 unchanged lines hidden --- 		139 void dmaWrite(Addr addr, int size, Event *event, uint8_t *data,
140 Tick delay = 0)
141 {
142 dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data, delay);
143 }
144
145 void dmaRead(Addr addr, int size, Event *event, uint8_t *data,
146 Tick delay = 0)

--- 19 unchanged lines hidden ---