dma_device.hh (13784:1941dc118243) dma_device.hh (13892:0182a0601f66)
1/*
2 * Copyright (c) 2012-2013, 2015, 2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 40 unchanged lines hidden (view full) ---

49#include <memory>
50
51#include "base/circlebuf.hh"
52#include "dev/io_device.hh"
53#include "params/DmaDevice.hh"
54#include "sim/drain.hh"
55#include "sim/system.hh"
56
1/*
2 * Copyright (c) 2012-2013, 2015, 2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 40 unchanged lines hidden (view full) ---

49#include <memory>
50
51#include "base/circlebuf.hh"
52#include "dev/io_device.hh"
53#include "params/DmaDevice.hh"
54#include "sim/drain.hh"
55#include "sim/system.hh"
56
57class ClockedObject;
58
57class DmaPort : public MasterPort, public Drainable
58{
59 private:
60
61 /**
62 * Take the first packet of the transmit list and attempt to send
63 * it as a timing request. If it is successful, schedule the
64 * sending of the next packet, otherwise remember that we are

--- 39 unchanged lines hidden (view full) ---

104
105 DmaReqState(Event *ce, Addr tb, Tick _delay)
106 : completionEvent(ce), totBytes(tb), numBytes(0), delay(_delay)
107 {}
108 };
109
110 public:
111 /** The device that owns this port. */
59class DmaPort : public MasterPort, public Drainable
60{
61 private:
62
63 /**
64 * Take the first packet of the transmit list and attempt to send
65 * it as a timing request. If it is successful, schedule the
66 * sending of the next packet, otherwise remember that we are

--- 39 unchanged lines hidden (view full) ---

106
107 DmaReqState(Event *ce, Addr tb, Tick _delay)
108 : completionEvent(ce), totBytes(tb), numBytes(0), delay(_delay)
109 {}
110 };
111
112 public:
113 /** The device that owns this port. */
112 MemObject *const device;
114 ClockedObject *const device;
113
114 /** The system that device/port are in. This is used to select which mode
115 * we are currently operating in. */
116 System *const sys;
117
118 /** Id for all requests */
119 const MasterID masterId;
120

--- 15 unchanged lines hidden (view full) ---

136
137 bool recvTimingResp(PacketPtr pkt) override;
138 void recvReqRetry() override;
139
140 void queueDma(PacketPtr pkt);
141
142 public:
143
115
116 /** The system that device/port are in. This is used to select which mode
117 * we are currently operating in. */
118 System *const sys;
119
120 /** Id for all requests */
121 const MasterID masterId;
122

--- 15 unchanged lines hidden (view full) ---

138
139 bool recvTimingResp(PacketPtr pkt) override;
140 void recvReqRetry() override;
141
142 void queueDma(PacketPtr pkt);
143
144 public:
145
144 DmaPort(MemObject *dev, System *s);
146 DmaPort(ClockedObject *dev, System *s);
145
146 RequestPtr dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
147 uint8_t *data, Tick delay, Request::Flags flag = 0);
148
149 bool dmaPending() const { return pendingCount > 0; }
150
151 DrainState drain() override;
152};

--- 349 unchanged lines hidden --- 		147
148 RequestPtr dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
149 uint8_t *data, Tick delay, Request::Flags flag = 0);
150
151 bool dmaPending() const { return pendingCount > 0; }
152
153 DrainState drain() override;
154};

--- 349 unchanged lines hidden ---