dma_device.hh (11168:f98eb2da15a4) dma_device.hh (11169:44b5c183c3cd)
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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129 uint32_t pendingCount;
130
131 /** If the port is currently waiting for a retry before it can
132 * send whatever it is that it's sending. */
133 bool inRetry;
134
135 protected:
136
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 120 unchanged lines hidden (view full) ---

129 uint32_t pendingCount;
130
131 /** If the port is currently waiting for a retry before it can
132 * send whatever it is that it's sending. */
133 bool inRetry;
134
135 protected:
136
137 bool recvTimingResp(PacketPtr pkt);
138 void recvReqRetry() ;
137 bool recvTimingResp(PacketPtr pkt) override;
138 void recvReqRetry() override;
139
140 void queueDma(PacketPtr pkt);
141
142 public:
143
144 DmaPort(MemObject *dev, System *s);
145
146 RequestPtr dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,

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170 void dmaRead(Addr addr, int size, Event *event, uint8_t *data,
171 Tick delay = 0)
172 {
173 dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay);
174 }
175
176 bool dmaPending() const { return dmaPort.dmaPending(); }
177
139
140 void queueDma(PacketPtr pkt);
141
142 public:
143
144 DmaPort(MemObject *dev, System *s);
145
146 RequestPtr dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,

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170 void dmaRead(Addr addr, int size, Event *event, uint8_t *data,
171 Tick delay = 0)
172 {
173 dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay);
174 }
175
176 bool dmaPending() const { return dmaPort.dmaPending(); }
177
178 virtual void init();
178 void init() override;
179
180 unsigned int cacheBlockSize() const { return sys->cacheLineSize(); }
181
179
180 unsigned int cacheBlockSize() const { return sys->cacheLineSize(); }
181
182 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
183 PortID idx = InvalidPortID);
182 BaseMasterPort &getMasterPort(const std::string &if_name,
183 PortID idx = InvalidPortID) override;
184
185};
186
187/**
188 * Buffered DMA engine helper class
189 *
190 * This class implements a simple DMA engine that feeds a FIFO
191 * buffer. The size of the buffer, the maximum number of pending

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185};
186
187/**
188 * Buffered DMA engine helper class
189 *
190 * This class implements a simple DMA engine that feeds a FIFO
191 * buffer. The size of the buffer, the maximum number of pending

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