dma_device.hh (10913:38dbdeea7f1f) | dma_device.hh (11010:034378be28a2) |
---|---|
1/* | 1/* |
2 * Copyright (c) 2012-2013 ARM Limited | 2 * Copyright (c) 2012-2013, 2015 ARM Limited |
3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 23 unchanged lines hidden (view full) --- 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Nathan Binkert | 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 23 unchanged lines hidden (view full) --- 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Nathan Binkert |
42 * Andreas Sandberg |
|
42 */ 43 44#ifndef __DEV_DMA_DEVICE_HH__ 45#define __DEV_DMA_DEVICE_HH__ 46 47#include <deque> | 43 */ 44 45#ifndef __DEV_DMA_DEVICE_HH__ 46#define __DEV_DMA_DEVICE_HH__ 47 48#include <deque> |
49#include <memory> |
|
48 | 50 |
51#include "base/circlebuf.hh" |
|
49#include "dev/io_device.hh" 50#include "params/DmaDevice.hh" 51#include "sim/drain.hh" 52#include "sim/system.hh" 53 54class DmaPort : public MasterPort, public Drainable 55{ 56 private: --- 42 unchanged lines hidden (view full) --- 99 /** Amount to delay completion of dma by */ 100 const Tick delay; 101 102 DmaReqState(Event *ce, Addr tb, Tick _delay) 103 : completionEvent(ce), totBytes(tb), numBytes(0), delay(_delay) 104 {} 105 }; 106 | 52#include "dev/io_device.hh" 53#include "params/DmaDevice.hh" 54#include "sim/drain.hh" 55#include "sim/system.hh" 56 57class DmaPort : public MasterPort, public Drainable 58{ 59 private: --- 42 unchanged lines hidden (view full) --- 102 /** Amount to delay completion of dma by */ 103 const Tick delay; 104 105 DmaReqState(Event *ce, Addr tb, Tick _delay) 106 : completionEvent(ce), totBytes(tb), numBytes(0), delay(_delay) 107 {} 108 }; 109 |
110 public: |
|
107 /** The device that owns this port. */ | 111 /** The device that owns this port. */ |
108 MemObject *device; | 112 MemObject *const device; |
109 | 113 |
110 /** Use a deque as we never do any insertion or removal in the middle */ 111 std::deque<PacketPtr> transmitList; 112 113 /** Event used to schedule a future sending from the transmit list. */ 114 EventWrapper<DmaPort, &DmaPort::sendDma> sendEvent; 115 | |
116 /** The system that device/port are in. This is used to select which mode 117 * we are currently operating in. */ | 114 /** The system that device/port are in. This is used to select which mode 115 * we are currently operating in. */ |
118 System *sys; | 116 System *const sys; |
119 120 /** Id for all requests */ 121 const MasterID masterId; 122 | 117 118 /** Id for all requests */ 119 const MasterID masterId; 120 |
121 protected: 122 /** Use a deque as we never do any insertion or removal in the middle */ 123 std::deque<PacketPtr> transmitList; 124 125 /** Event used to schedule a future sending from the transmit list. */ 126 EventWrapper<DmaPort, &DmaPort::sendDma> sendEvent; 127 |
|
123 /** Number of outstanding packets the dma port has. */ 124 uint32_t pendingCount; 125 126 /** If the port is currently waiting for a retry before it can 127 * send whatever it is that it's sending. */ 128 bool inRetry; 129 130 protected: --- 43 unchanged lines hidden (view full) --- 174 175 unsigned int cacheBlockSize() const { return sys->cacheLineSize(); } 176 177 virtual BaseMasterPort &getMasterPort(const std::string &if_name, 178 PortID idx = InvalidPortID); 179 180}; 181 | 128 /** Number of outstanding packets the dma port has. */ 129 uint32_t pendingCount; 130 131 /** If the port is currently waiting for a retry before it can 132 * send whatever it is that it's sending. */ 133 bool inRetry; 134 135 protected: --- 43 unchanged lines hidden (view full) --- 179 180 unsigned int cacheBlockSize() const { return sys->cacheLineSize(); } 181 182 virtual BaseMasterPort &getMasterPort(const std::string &if_name, 183 PortID idx = InvalidPortID); 184 185}; 186 |
187/** 188 * Buffered DMA engine helper class 189 * 190 * This class implements a simple DMA engine that feeds a FIFO 191 * buffer. The size of the buffer, the maximum number of pending 192 * requests and the maximum request size are all set when the engine 193 * is instantiated. 194 * 195 * An <i>asynchronous</i> transfer of a <i>block</i> of data 196 * (designated by a start address and a size) is started by calling 197 * the startFill() method. The DMA engine will aggressively try to 198 * keep the internal FIFO full. As soon as there is room in the FIFO 199 * for more data <i>and</i> there are free request slots, a new fill 200 * will be started. 201 * 202 * Data in the FIFO can be read back using the get() and tryGet() 203 * methods. Both request a block of data from the FIFO. However, get() 204 * panics if the block cannot be satisfied, while tryGet() simply 205 * returns false. The latter call makes it possible to implement 206 * custom buffer underrun handling. 207 * 208 * A simple use case would be something like this: 209 * \code{.cpp} 210 * // Create a DMA engine with a 1KiB buffer. Issue up to 8 concurrent 211 * // uncacheable 64 byte (maximum) requests. 212 * DmaReadFifo *dma = new DmaReadFifo(port, 1024, 64, 8, 213 * Request::UNCACHEABLE); 214 * 215 * // Start copying 4KiB data from 0xFF000000 216 * dma->startFill(0xFF000000, 0x1000); 217 * 218 * // Some time later when there is data in the FIFO. 219 * uint8_t data[8]; 220 * dma->get(data, sizeof(data)) 221 * \endcode 222 * 223 * 224 * The DMA engine allows new blocks to be requested as soon as the 225 * last request for a block has been sent (i.e., there is no need to 226 * wait for pending requests to complete). This can be queried with 227 * the atEndOfBlock() method and more advanced implementations may 228 * override the onEndOfBlock() callback. 229 */ 230class DmaReadFifo : public Drainable, public Serializable 231{ 232 public: 233 DmaReadFifo(DmaPort &port, size_t size, 234 unsigned max_req_size, 235 unsigned max_pending, 236 Request::Flags flags = 0); 237 238 ~DmaReadFifo(); 239 240 public: // Serializable 241 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 242 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 243 244 public: // Drainable 245 DrainState drain() M5_ATTR_OVERRIDE; 246 247 public: // FIFO access 248 /** 249 * @{ 250 * @name FIFO access 251 */ 252 /** 253 * Try to read data from the FIFO. 254 * 255 * This method reads len bytes of data from the FIFO and stores 256 * them in the memory location pointed to by dst. The method 257 * fails, and no data is written to the buffer, if the FIFO 258 * doesn't contain enough data to satisfy the request. 259 * 260 * @param dst Pointer to a destination buffer 261 * @param len Amount of data to read. 262 * @return true on success, false otherwise. 263 */ 264 bool tryGet(uint8_t *dst, size_t len); 265 266 template<typename T> 267 bool tryGet(T &value) { 268 return tryGet(static_cast<T *>(&value), sizeof(T)); 269 }; 270 271 /** 272 * Read data from the FIFO and panic on failure. 273 * 274 * @see tryGet() 275 * 276 * @param dst Pointer to a destination buffer 277 * @param len Amount of data to read. 278 */ 279 void get(uint8_t *dst, size_t len); 280 281 template<typename T> 282 T get() { 283 T value; 284 get(static_cast<uint8_t *>(&value), sizeof(T)); 285 return value; 286 }; 287 288 /** Get the amount of data stored in the FIFO */ 289 size_t size() const { return buffer.size(); } 290 /** Flush the FIFO */ 291 void flush() { buffer.flush(); } 292 293 /** @} */ 294 public: // FIFO fill control 295 /** 296 * @{ 297 * @name FIFO fill control 298 */ 299 /** 300 * Start filling the FIFO. 301 * 302 * @warn It's considered an error to call start on an active DMA 303 * engine unless the last request from the active block has been 304 * sent (i.e., atEndOfBlock() is true). 305 * 306 * @param start Physical address to copy from. 307 * @param size Size of the block to copy. 308 */ 309 void startFill(Addr start, size_t size); 310 311 /** 312 * Stop the DMA engine. 313 * 314 * Stop filling the FIFO and ignore incoming responses for pending 315 * requests. The onEndOfBlock() callback will not be called after 316 * this method has been invoked. However, once the last response 317 * has been received, the onIdle() callback will still be called. 318 */ 319 void stopFill(); 320 321 /** 322 * Has the DMA engine sent out the last request for the active 323 * block? 324 */ 325 bool atEndOfBlock() const { 326 return nextAddr == endAddr; 327 } 328 329 /** 330 * Is the DMA engine active (i.e., are there still in-flight 331 * accesses)? 332 */ 333 bool isActive() const { 334 return !(pendingRequests.empty() && atEndOfBlock()); 335 } 336 337 /** @} */ 338 protected: // Callbacks 339 /** 340 * @{ 341 * @name Callbacks 342 */ 343 /** 344 * End of block callback 345 * 346 * This callback is called <i>once</i> after the last access in a 347 * block has been sent. It is legal for a derived class to call 348 * startFill() from this method to initiate a transfer. 349 */ 350 virtual void onEndOfBlock() {}; 351 352 /** 353 * Last response received callback 354 * 355 * This callback is called when the DMA engine becomes idle (i.e., 356 * there are no pending requests). 357 * 358 * It is possible for a DMA engine to reach the end of block and 359 * become idle at the same tick. In such a case, the 360 * onEndOfBlock() callback will be called first. This callback 361 * will <i>NOT</i> be called if that callback initiates a new DMA transfer. 362 */ 363 virtual void onIdle() {}; 364 365 /** @} */ 366 private: // Configuration 367 /** Maximum request size in bytes */ 368 const Addr maxReqSize; 369 /** Maximum FIFO size in bytes */ 370 const size_t fifoSize; 371 /** Request flags */ 372 const Request::Flags reqFlags; 373 374 DmaPort &port; 375 376 private: 377 class DmaDoneEvent : public Event 378 { 379 public: 380 DmaDoneEvent(DmaReadFifo *_parent, size_t max_size); 381 382 void kill(); 383 void cancel(); 384 bool canceled() const { return _canceled; } 385 void reset(size_t size); 386 void process(); 387 388 bool done() const { return _done; } 389 size_t requestSize() const { return _requestSize; } 390 const uint8_t *data() const { return _data.data(); } 391 uint8_t *data() { return _data.data(); } 392 393 private: 394 DmaReadFifo *parent; 395 bool _done; 396 bool _canceled; 397 size_t _requestSize; 398 std::vector<uint8_t> _data; 399 }; 400 401 typedef std::unique_ptr<DmaDoneEvent> DmaDoneEventUPtr; 402 403 /** 404 * DMA request done, handle incoming data and issue new 405 * request. 406 */ 407 void dmaDone(); 408 409 /** Handle pending requests that have been flagged as done. */ 410 void handlePending(); 411 412 /** Try to issue new DMA requests */ 413 void resumeFill(); 414 415 private: // Internal state 416 Fifo<uint8_t> buffer; 417 418 Addr nextAddr; 419 Addr endAddr; 420 421 std::deque<DmaDoneEventUPtr> pendingRequests; 422 std::deque<DmaDoneEventUPtr> freeRequests; 423}; 424 |
|
182#endif // __DEV_DMA_DEVICE_HH__ | 425#endif // __DEV_DMA_DEVICE_HH__ |