dma_device.hh (10713:eddb533708cb) dma_device.hh (10912:b99a6662d7c2)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46
47#include <deque>
48
49#include "dev/io_device.hh"
50#include "params/DmaDevice.hh"
51#include "sim/drain.hh"
52#include "sim/system.hh"
53
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46
47#include <deque>
48
49#include "dev/io_device.hh"
50#include "params/DmaDevice.hh"
51#include "sim/drain.hh"
52#include "sim/system.hh"
53
54class DmaPort : public MasterPort
54class DmaPort : public MasterPort, public Drainable
55{
56 private:
57
58 /**
59 * Take the first packet of the transmit list and attempt to send
60 * it as a timing request. If it is successful, schedule the
61 * sending of the next packet, otherwise remember that we are
62 * waiting for a retry.

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171 {
172 dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay);
173 }
174
175 bool dmaPending() const { return dmaPort.dmaPending(); }
176
177 virtual void init();
178
55{
56 private:
57
58 /**
59 * Take the first packet of the transmit list and attempt to send
60 * it as a timing request. If it is successful, schedule the
61 * sending of the next packet, otherwise remember that we are
62 * waiting for a retry.

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171 {
172 dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay);
173 }
174
175 bool dmaPending() const { return dmaPort.dmaPending(); }
176
177 virtual void init();
178
179 unsigned int drain(DrainManager *drainManger);
180
181 unsigned int cacheBlockSize() const { return sys->cacheLineSize(); }
182
183 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
184 PortID idx = InvalidPortID);
185
186};
187
188#endif // __DEV_DMA_DEVICE_HH__
179 unsigned int cacheBlockSize() const { return sys->cacheLineSize(); }
180
181 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
182 PortID idx = InvalidPortID);
183
184};
185
186#endif // __DEV_DMA_DEVICE_HH__