1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Nathan Binkert
42 */
43
44#ifndef __DEV_DMA_DEVICE_HH__
45#define __DEV_DMA_DEVICE_HH__
46
47#include <deque>
48
49#include "dev/io_device.hh"
50#include "params/DmaDevice.hh"
51
52class DmaPort : public MasterPort
53{
54 protected:
55 struct DmaReqState : public Packet::SenderState
56 {
57 /** Event to call on the device when this transaction (all packets)
58 * complete. */
59 Event *completionEvent;
60
61 /** Total number of bytes that this transaction involves. */
62 Addr totBytes;
63
64 /** Number of bytes that have been acked for this transaction. */
65 Addr numBytes;
66
67 /** Amount to delay completion of dma by */
68 Tick delay;
69
70 DmaReqState(Event *ce, Addr tb, Tick _delay)
71 : completionEvent(ce), totBytes(tb), numBytes(0), delay(_delay)
72 {}
73 };
74
75 MemObject *device;
76
77 /** Use a deque as we never to any insertion or removal in the middle */
78 std::deque<PacketPtr> transmitList;
79
80 /** The system that device/port are in. This is used to select which mode
81 * we are currently operating in. */
82 System *sys;
83
84 /** Id for all requests */
85 MasterID masterId;
86
87 /** Number of outstanding packets the dma port has. */
88 uint32_t pendingCount;
89
90 /** If we need to drain, keep the drain event around until we're done
91 * here.*/
92 Event *drainEvent;
93
94 /** If the port is currently waiting for a retry before it can
95 * send whatever it is that it's sending. */
96 bool inRetry;
97
98 /**
99 * Handle a response packet by updating the corresponding DMA
100 * request state to reflect the bytes received, and also update
101 * the pending request counter. If the DMA request that this
102 * packet is part of is complete, then signal the completion event
103 * if present, potentially with a delay added to it.
104 *
105 * @param pkt Response packet to handler
106 * @param delay Additional delay for scheduling the completion event
107 */
108 void handleResp(PacketPtr pkt, Tick delay = 0);
109
110 bool recvTimingResp(PacketPtr pkt);
111 void recvRetry() ;
112
113 void queueDma(PacketPtr pkt);
114 void sendDma();
115
116 public:
117
118 DmaPort(MemObject *dev, System *s);
119
120 void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
121 uint8_t *data, Tick delay, Request::Flags flag = 0);
122
123 bool dmaPending() const { return pendingCount > 0; }
124
125 unsigned cacheBlockSize() const { return peerBlockSize(); }
126 unsigned int drain(Event *de);
127};
128
129class DmaDevice : public PioDevice
130{
131 protected:
132 DmaPort dmaPort;
133
134 public:
135 typedef DmaDeviceParams Params;
136 DmaDevice(const Params *p);
137 virtual ~DmaDevice() { }
138
139 void dmaWrite(Addr addr, int size, Event *event, uint8_t *data,
140 Tick delay = 0)
141 {
142 dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data, delay);
143 }
144
145 void dmaRead(Addr addr, int size, Event *event, uint8_t *data,
146 Tick delay = 0)
147 {
148 dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay);
149 }
150
151 bool dmaPending() { return dmaPort.dmaPending(); }
152
153 virtual void init();
154
155 virtual unsigned int drain(Event *de);
156
157 unsigned cacheBlockSize() const { return dmaPort.cacheBlockSize(); }
158
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Nathan Binkert
42 */
43
44#ifndef __DEV_DMA_DEVICE_HH__
45#define __DEV_DMA_DEVICE_HH__
46
47#include <deque>
48
49#include "dev/io_device.hh"
50#include "params/DmaDevice.hh"
51
52class DmaPort : public MasterPort
53{
54 protected:
55 struct DmaReqState : public Packet::SenderState
56 {
57 /** Event to call on the device when this transaction (all packets)
58 * complete. */
59 Event *completionEvent;
60
61 /** Total number of bytes that this transaction involves. */
62 Addr totBytes;
63
64 /** Number of bytes that have been acked for this transaction. */
65 Addr numBytes;
66
67 /** Amount to delay completion of dma by */
68 Tick delay;
69
70 DmaReqState(Event *ce, Addr tb, Tick _delay)
71 : completionEvent(ce), totBytes(tb), numBytes(0), delay(_delay)
72 {}
73 };
74
75 MemObject *device;
76
77 /** Use a deque as we never to any insertion or removal in the middle */
78 std::deque<PacketPtr> transmitList;
79
80 /** The system that device/port are in. This is used to select which mode
81 * we are currently operating in. */
82 System *sys;
83
84 /** Id for all requests */
85 MasterID masterId;
86
87 /** Number of outstanding packets the dma port has. */
88 uint32_t pendingCount;
89
90 /** If we need to drain, keep the drain event around until we're done
91 * here.*/
92 Event *drainEvent;
93
94 /** If the port is currently waiting for a retry before it can
95 * send whatever it is that it's sending. */
96 bool inRetry;
97
98 /**
99 * Handle a response packet by updating the corresponding DMA
100 * request state to reflect the bytes received, and also update
101 * the pending request counter. If the DMA request that this
102 * packet is part of is complete, then signal the completion event
103 * if present, potentially with a delay added to it.
104 *
105 * @param pkt Response packet to handler
106 * @param delay Additional delay for scheduling the completion event
107 */
108 void handleResp(PacketPtr pkt, Tick delay = 0);
109
110 bool recvTimingResp(PacketPtr pkt);
111 void recvRetry() ;
112
113 void queueDma(PacketPtr pkt);
114 void sendDma();
115
116 public:
117
118 DmaPort(MemObject *dev, System *s);
119
120 void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
121 uint8_t *data, Tick delay, Request::Flags flag = 0);
122
123 bool dmaPending() const { return pendingCount > 0; }
124
125 unsigned cacheBlockSize() const { return peerBlockSize(); }
126 unsigned int drain(Event *de);
127};
128
129class DmaDevice : public PioDevice
130{
131 protected:
132 DmaPort dmaPort;
133
134 public:
135 typedef DmaDeviceParams Params;
136 DmaDevice(const Params *p);
137 virtual ~DmaDevice() { }
138
139 void dmaWrite(Addr addr, int size, Event *event, uint8_t *data,
140 Tick delay = 0)
141 {
142 dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data, delay);
143 }
144
145 void dmaRead(Addr addr, int size, Event *event, uint8_t *data,
146 Tick delay = 0)
147 {
148 dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay);
149 }
150
151 bool dmaPending() { return dmaPort.dmaPending(); }
152
153 virtual void init();
154
155 virtual unsigned int drain(Event *de);
156
157 unsigned cacheBlockSize() const { return dmaPort.cacheBlockSize(); }
158
|