1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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180 unsigned int cacheBlockSize() const { return sys->cacheLineSize(); }
181
182 BaseMasterPort &getMasterPort(const std::string &if_name,
183 PortID idx = InvalidPortID) override;
184
185};
186
187/**
188 * Buffered DMA engine helper class
189 *
190 * This class implements a simple DMA engine that feeds a FIFO
191 * buffer. The size of the buffer, the maximum number of pending
192 * requests and the maximum request size are all set when the engine
193 * is instantiated.
194 *
195 * An <i>asynchronous</i> transfer of a <i>block</i> of data

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