dma_device.cc (9133:82491f9ed266) dma_device.cc (9152:86c0e6ca5e7c)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Nathan Binkert
42 */
43
44#include "base/chunk_generator.hh"
45#include "debug/DMA.hh"
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Nathan Binkert
42 */
43
44#include "base/chunk_generator.hh"
45#include "debug/DMA.hh"
46#include "debug/Drain.hh"
46#include "dev/dma_device.hh"
47#include "sim/system.hh"
48
49DmaPort::DmaPort(MemObject *dev, System *s, Tick min_backoff, Tick max_backoff)
50 : MasterPort(dev->name() + ".dma", dev), device(dev), sys(s),
51 masterId(s->getMasterId(dev->name())),
52 pendingCount(0), drainEvent(NULL),
53 backoffTime(0), minBackoffDelay(min_backoff),

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98 else
99 state->completionEvent->process();
100 }
101 delete state;
102 }
103 delete pkt->req;
104 delete pkt;
105
47#include "dev/dma_device.hh"
48#include "sim/system.hh"
49
50DmaPort::DmaPort(MemObject *dev, System *s, Tick min_backoff, Tick max_backoff)
51 : MasterPort(dev->name() + ".dma", dev), device(dev), sys(s),
52 masterId(s->getMasterId(dev->name())),
53 pendingCount(0), drainEvent(NULL),
54 backoffTime(0), minBackoffDelay(min_backoff),

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99 else
100 state->completionEvent->process();
101 }
102 delete state;
103 }
104 delete pkt->req;
105 delete pkt;
106
106 if (pendingCount == 0 && drainEvent) {
107 if (pendingCount == 0 && transmitList.empty() && drainEvent) {
107 drainEvent->process();
108 drainEvent = NULL;
109 }
110 } else {
111 panic("Got packet without sender state... huh?\n");
112 }
113
114 return true;

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137 else
138 changeState(Drained);
139 return count;
140}
141
142unsigned int
143DmaPort::drain(Event *de)
144{
108 drainEvent->process();
109 drainEvent = NULL;
110 }
111 } else {
112 panic("Got packet without sender state... huh?\n");
113 }
114
115 return true;

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138 else
139 changeState(Drained);
140 return count;
141}
142
143unsigned int
144DmaPort::drain(Event *de)
145{
145 if (pendingCount == 0)
146 if (transmitList.empty() && pendingCount == 0)
146 return 0;
147 drainEvent = de;
147 return 0;
148 drainEvent = de;
149 DPRINTF(Drain, "DmaPort not drained\n");
148 return 1;
149}
150
151void
152DmaPort::recvRetry()
153{
154 assert(transmitList.size());
155 bool result = true;

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177 transmitList.size(), backoffTime, inRetry,
178 backoffEvent.scheduled());
179}
180
181void
182DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
183 uint8_t *data, Tick delay, Request::Flags flag)
184{
150 return 1;
151}
152
153void
154DmaPort::recvRetry()
155{
156 assert(transmitList.size());
157 bool result = true;

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179 transmitList.size(), backoffTime, inRetry,
180 backoffEvent.scheduled());
181}
182
183void
184DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
185 uint8_t *data, Tick delay, Request::Flags flag)
186{
185 assert(device->getState() == SimObject::Running);
186
187 DmaReqState *reqState = new DmaReqState(event, size, delay);
188
189
190 DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size,
191 event ? event->scheduled() : -1 );
192 for (ChunkGenerator gen(addr, size, peerBlockSize());
193 !gen.done(); gen.next()) {
194 Request *req = new Request(gen.addr(), gen.size(), flag, masterId);

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282 }
283 delete state;
284 delete pkt->req;
285 }
286 pendingCount--;
287 assert(pendingCount >= 0);
288 delete pkt;
289
187 DmaReqState *reqState = new DmaReqState(event, size, delay);
188
189
190 DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size,
191 event ? event->scheduled() : -1 );
192 for (ChunkGenerator gen(addr, size, peerBlockSize());
193 !gen.done(); gen.next()) {
194 Request *req = new Request(gen.addr(), gen.size(), flag, masterId);

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282 }
283 delete state;
284 delete pkt->req;
285 }
286 pendingCount--;
287 assert(pendingCount >= 0);
288 delete pkt;
289
290 if (pendingCount == 0 && drainEvent) {
290 if (pendingCount == 0 && transmitList.empty() && drainEvent) {
291 DPRINTF(Drain, "DmaPort done draining, processing drain event\n");
291 drainEvent->process();
292 drainEvent = NULL;
293 }
294
295 } else
296 panic("Unknown memory command state.");
297}
298

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293 drainEvent = NULL;
294 }
295
296 } else
297 panic("Unknown memory command state.");
298}
299

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