dma_device.cc (13892:0182a0601f66) dma_device.cc (13930:c5e728ccd2e2)
1/*
1/*
2 * Copyright (c) 2012, 2015, 2017 ARM Limited
2 * Copyright (c) 2012, 2015, 2017, 2019 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 38 unchanged lines hidden (view full) ---

49
50#include "base/chunk_generator.hh"
51#include "debug/DMA.hh"
52#include "debug/Drain.hh"
53#include "mem/port_proxy.hh"
54#include "sim/clocked_object.hh"
55#include "sim/system.hh"
56
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 38 unchanged lines hidden (view full) ---

49
50#include "base/chunk_generator.hh"
51#include "debug/DMA.hh"
52#include "debug/Drain.hh"
53#include "mem/port_proxy.hh"
54#include "sim/clocked_object.hh"
55#include "sim/system.hh"
56
57DmaPort::DmaPort(ClockedObject *dev, System *s)
57DmaPort::DmaPort(ClockedObject *dev, System *s,
58 uint32_t sid, uint32_t ssid)
58 : MasterPort(dev->name() + ".dma", dev),
59 device(dev), sys(s), masterId(s->getMasterId(dev)),
60 sendEvent([this]{ sendDma(); }, dev->name()),
59 : MasterPort(dev->name() + ".dma", dev),
60 device(dev), sys(s), masterId(s->getMasterId(dev)),
61 sendEvent([this]{ sendDma(); }, dev->name()),
61 pendingCount(0), inRetry(false)
62 pendingCount(0), inRetry(false),
63 defaultSid(sid),
64 defaultSSid(ssid)
62{ }
63
64void
65DmaPort::handleResp(PacketPtr pkt, Tick delay)
66{
67 // should always see a response with a sender state
68 assert(pkt->isResponse());
69

--- 42 unchanged lines hidden (view full) ---

112 !(pkt->cacheResponding() && !pkt->hasSharers()));
113
114 handleResp(pkt);
115
116 return true;
117}
118
119DmaDevice::DmaDevice(const Params *p)
65{ }
66
67void
68DmaPort::handleResp(PacketPtr pkt, Tick delay)
69{
70 // should always see a response with a sender state
71 assert(pkt->isResponse());
72

--- 42 unchanged lines hidden (view full) ---

115 !(pkt->cacheResponding() && !pkt->hasSharers()));
116
117 handleResp(pkt);
118
119 return true;
120}
121
122DmaDevice::DmaDevice(const Params *p)
120 : PioDevice(p), dmaPort(this, sys)
123 : PioDevice(p), dmaPort(this, sys, p->sid, p->ssid)
121{ }
122
123void
124DmaDevice::init()
125{
126 if (!dmaPort.isConnected())
127 panic("DMA port of %s not connected to anything!", name());
128 PioDevice::init();

--- 14 unchanged lines hidden (view full) ---

143DmaPort::recvReqRetry()
144{
145 assert(transmitList.size());
146 trySendTimingReq();
147}
148
149RequestPtr
150DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
124{ }
125
126void
127DmaDevice::init()
128{
129 if (!dmaPort.isConnected())
130 panic("DMA port of %s not connected to anything!", name());
131 PioDevice::init();

--- 14 unchanged lines hidden (view full) ---

146DmaPort::recvReqRetry()
147{
148 assert(transmitList.size());
149 trySendTimingReq();
150}
151
152RequestPtr
153DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
151 uint8_t *data, Tick delay, Request::Flags flag)
154 uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay,
155 Request::Flags flag)
152{
153 // one DMA request sender state for every action, that is then
154 // split into many requests and packets based on the block size,
155 // i.e. cache line size
156 DmaReqState *reqState = new DmaReqState(event, size, delay);
157
158 // (functionality added for Table Walker statistics)
159 // We're only interested in this when there will only be one request.

--- 4 unchanged lines hidden (view full) ---

164 DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size,
165 event ? event->scheduled() : -1);
166 for (ChunkGenerator gen(addr, size, sys->cacheLineSize());
167 !gen.done(); gen.next()) {
168
169 req = std::make_shared<Request>(
170 gen.addr(), gen.size(), flag, masterId);
171
156{
157 // one DMA request sender state for every action, that is then
158 // split into many requests and packets based on the block size,
159 // i.e. cache line size
160 DmaReqState *reqState = new DmaReqState(event, size, delay);
161
162 // (functionality added for Table Walker statistics)
163 // We're only interested in this when there will only be one request.

--- 4 unchanged lines hidden (view full) ---

168 DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size,
169 event ? event->scheduled() : -1);
170 for (ChunkGenerator gen(addr, size, sys->cacheLineSize());
171 !gen.done(); gen.next()) {
172
173 req = std::make_shared<Request>(
174 gen.addr(), gen.size(), flag, masterId);
175
176 req->setStreamId(sid);
177 req->setSubStreamId(ssid);
178
172 req->taskId(ContextSwitchTaskId::DMA);
173 PacketPtr pkt = new Packet(req, cmd);
174
175 // Increment the data pointer on a write
176 if (data)
177 pkt->dataStatic(data + gen.complete());
178
179 pkt->senderState = reqState;

--- 6 unchanged lines hidden (view full) ---

186 // in zero time also initiate the sending of the packets we have
187 // just created, for atomic this involves actually completing all
188 // the requests
189 sendDma();
190
191 return req;
192}
193
179 req->taskId(ContextSwitchTaskId::DMA);
180 PacketPtr pkt = new Packet(req, cmd);
181
182 // Increment the data pointer on a write
183 if (data)
184 pkt->dataStatic(data + gen.complete());
185
186 pkt->senderState = reqState;

--- 6 unchanged lines hidden (view full) ---

193 // in zero time also initiate the sending of the packets we have
194 // just created, for atomic this involves actually completing all
195 // the requests
196 sendDma();
197
198 return req;
199}
200
201RequestPtr
202DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
203 uint8_t *data, Tick delay, Request::Flags flag)
204{
205 return dmaAction(cmd, addr, size, event, data,
206 defaultSid, defaultSSid, delay, flag);
207}
208
194void
195DmaPort::queueDma(PacketPtr pkt)
196{
197 transmitList.push_back(pkt);
198
199 // remember that we have another packet pending, this will only be
200 // decremented once a response comes back
201 pendingCount++;

--- 65 unchanged lines hidden (view full) ---

267DmaDevice::getPort(const std::string &if_name, PortID idx)
268{
269 if (if_name == "dma") {
270 return dmaPort;
271 }
272 return PioDevice::getPort(if_name, idx);
273}
274
209void
210DmaPort::queueDma(PacketPtr pkt)
211{
212 transmitList.push_back(pkt);
213
214 // remember that we have another packet pending, this will only be
215 // decremented once a response comes back
216 pendingCount++;

--- 65 unchanged lines hidden (view full) ---

282DmaDevice::getPort(const std::string &if_name, PortID idx)
283{
284 if (if_name == "dma") {
285 return dmaPort;
286 }
287 return PioDevice::getPort(if_name, idx);
288}
289
275
276
277
278
279DmaReadFifo::DmaReadFifo(DmaPort &_port, size_t size,
280 unsigned max_req_size,
281 unsigned max_pending,
282 Request::Flags flags)
283 : maxReqSize(max_req_size), fifoSize(size),
284 reqFlags(flags), port(_port),
285 buffer(size),
286 nextAddr(0), endAddr(0)

--- 225 unchanged lines hidden --- 		290DmaReadFifo::DmaReadFifo(DmaPort &_port, size_t size,
291 unsigned max_req_size,
292 unsigned max_pending,
293 Request::Flags flags)
294 : maxReqSize(max_req_size), fifoSize(size),
295 reqFlags(flags), port(_port),
296 buffer(size),
297 nextAddr(0), endAddr(0)

--- 225 unchanged lines hidden ---