dma_device.cc (10913:38dbdeea7f1f) dma_device.cc (11010:034378be28a2)
1/*
1/*
2 * Copyright (c) 2012 ARM Limited
2 * Copyright (c) 2012, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Nathan Binkert
42 * Andreas Hansson
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 24 unchanged lines hidden (view full) ---

35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Nathan Binkert
42 * Andreas Hansson
43 * Andreas Sandberg
43 */
44
44 */
45
46#include "dev/dma_device.hh"
47
48#include <utility>
49
45#include "base/chunk_generator.hh"
46#include "debug/DMA.hh"
47#include "debug/Drain.hh"
50#include "base/chunk_generator.hh"
51#include "debug/DMA.hh"
52#include "debug/Drain.hh"
48#include "dev/dma_device.hh"
49#include "sim/system.hh"
50
51DmaPort::DmaPort(MemObject *dev, System *s)
53#include "sim/system.hh"
54
55DmaPort::DmaPort(MemObject *dev, System *s)
52 : MasterPort(dev->name() + ".dma", dev), device(dev), sendEvent(this),
53 sys(s), masterId(s->getMasterId(dev->name())),
54 pendingCount(0), inRetry(false)
56 : MasterPort(dev->name() + ".dma", dev),
57 device(dev), sys(s), masterId(s->getMasterId(dev->name())),
58 sendEvent(this), pendingCount(0), inRetry(false)
55{ }
56
57void
58DmaPort::handleResp(PacketPtr pkt, Tick delay)
59{
60 // should always see a response with a sender state
61 assert(pkt->isResponse());
62

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257BaseMasterPort &
258DmaDevice::getMasterPort(const std::string &if_name, PortID idx)
259{
260 if (if_name == "dma") {
261 return dmaPort;
262 }
263 return PioDevice::getMasterPort(if_name, idx);
264}
59{ }
60
61void
62DmaPort::handleResp(PacketPtr pkt, Tick delay)
63{
64 // should always see a response with a sender state
65 assert(pkt->isResponse());
66

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261BaseMasterPort &
262DmaDevice::getMasterPort(const std::string &if_name, PortID idx)
263{
264 if (if_name == "dma") {
265 return dmaPort;
266 }
267 return PioDevice::getMasterPort(if_name, idx);
268}
269
270
271
272
273
274DmaReadFifo::DmaReadFifo(DmaPort &_port, size_t size,
275 unsigned max_req_size,
276 unsigned max_pending,
277 Request::Flags flags)
278 : maxReqSize(max_req_size), fifoSize(size),
279 reqFlags(flags), port(_port),
280 buffer(size),
281 nextAddr(0), endAddr(0)
282{
283 freeRequests.resize(max_pending);
284 for (auto &e : freeRequests)
285 e.reset(new DmaDoneEvent(this, max_req_size));
286
287}
288
289DmaReadFifo::~DmaReadFifo()
290{
291 for (auto &p : pendingRequests) {
292 DmaDoneEvent *e(p.release());
293
294 if (e->done()) {
295 delete e;
296 } else {
297 // We can't kill in-flight DMAs, so we'll just transfer
298 // ownership to the event queue so that they get freed
299 // when they are done.
300 e->kill();
301 }
302 }
303}
304
305void
306DmaReadFifo::serialize(CheckpointOut &cp) const
307{
308 assert(pendingRequests.empty());
309
310 SERIALIZE_CONTAINER(buffer);
311 SERIALIZE_SCALAR(endAddr);
312 SERIALIZE_SCALAR(nextAddr);
313}
314
315void
316DmaReadFifo::unserialize(CheckpointIn &cp)
317{
318 UNSERIALIZE_CONTAINER(buffer);
319 UNSERIALIZE_SCALAR(endAddr);
320 UNSERIALIZE_SCALAR(nextAddr);
321}
322
323bool
324DmaReadFifo::tryGet(uint8_t *dst, size_t len)
325{
326 if (buffer.size() >= len) {
327 buffer.read(dst, len);
328 resumeFill();
329 return true;
330 } else {
331 return false;
332 }
333}
334
335void
336DmaReadFifo::get(uint8_t *dst, size_t len)
337{
338 const bool success(tryGet(dst, len));
339 panic_if(!success, "Buffer underrun in DmaReadFifo::get()\n");
340}
341
342void
343DmaReadFifo::startFill(Addr start, size_t size)
344{
345 assert(atEndOfBlock());
346
347 nextAddr = start;
348 endAddr = start + size;
349 resumeFill();
350}
351
352void
353DmaReadFifo::stopFill()
354{
355 // Prevent new DMA requests by setting the next address to the end
356 // address. Pending requests will still complete.
357 nextAddr = endAddr;
358
359 // Flag in-flight accesses as canceled. This prevents their data
360 // from being written to the FIFO.
361 for (auto &p : pendingRequests)
362 p->cancel();
363}
364
365void
366DmaReadFifo::resumeFill()
367{
368 // Don't try to fetch more data if we are draining. This ensures
369 // that the DMA engine settles down before we checkpoint it.
370 if (drainState() == DrainState::Draining)
371 return;
372
373 const bool old_eob(atEndOfBlock());
374 size_t size_pending(0);
375 for (auto &e : pendingRequests)
376 size_pending += e->requestSize();
377
378 while (!freeRequests.empty() && !atEndOfBlock()) {
379 const size_t req_size(std::min(maxReqSize, endAddr - nextAddr));
380 if (buffer.size() + size_pending + req_size > fifoSize)
381 break;
382
383 DmaDoneEventUPtr event(std::move(freeRequests.front()));
384 freeRequests.pop_front();
385 assert(event);
386
387 event->reset(req_size);
388 port.dmaAction(MemCmd::ReadReq, nextAddr, req_size, event.get(),
389 event->data(), 0, reqFlags);
390 nextAddr += req_size;
391 size_pending += req_size;
392
393 pendingRequests.emplace_back(std::move(event));
394 }
395
396 // EOB can be set before a call to dmaDone() if in-flight accesses
397 // have been canceled.
398 if (!old_eob && atEndOfBlock())
399 onEndOfBlock();
400}
401
402void
403DmaReadFifo::dmaDone()
404{
405 const bool old_active(isActive());
406
407 handlePending();
408 resumeFill();
409
410 if (!old_active && isActive())
411 onIdle();
412}
413
414void
415DmaReadFifo::handlePending()
416{
417 while (!pendingRequests.empty() && pendingRequests.front()->done()) {
418 // Get the first finished pending request
419 DmaDoneEventUPtr event(std::move(pendingRequests.front()));
420 pendingRequests.pop_front();
421
422 if (!event->canceled())
423 buffer.write(event->data(), event->requestSize());
424
425 // Move the event to the list of free requests
426 freeRequests.emplace_back(std::move(event));
427 }
428
429 if (pendingRequests.empty())
430 signalDrainDone();
431}
432
433
434
435DrainState
436DmaReadFifo::drain()
437{
438 return pendingRequests.empty() ? DrainState::Drained : DrainState::Draining;
439}
440
441
442DmaReadFifo::DmaDoneEvent::DmaDoneEvent(DmaReadFifo *_parent,
443 size_t max_size)
444 : parent(_parent), _done(false), _canceled(false), _data(max_size, 0)
445{
446}
447
448void
449DmaReadFifo::DmaDoneEvent::kill()
450{
451 parent = nullptr;
452 setFlags(AutoDelete);
453}
454
455void
456DmaReadFifo::DmaDoneEvent::cancel()
457{
458 _canceled = true;
459}
460
461void
462DmaReadFifo::DmaDoneEvent::reset(size_t size)
463{
464 assert(size <= _data.size());
465 _done = false;
466 _canceled = false;
467 _requestSize = size;
468}
469
470void
471DmaReadFifo::DmaDoneEvent::process()
472{
473 if (!parent)
474 return;
475
476 assert(!_done);
477 _done = true;
478 parent->dmaDone();
479}