dma_device.cc (10912:b99a6662d7c2) dma_device.cc (10913:38dbdeea7f1f)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46#include "debug/DMA.hh"
47#include "debug/Drain.hh"
48#include "dev/dma_device.hh"
49#include "sim/system.hh"
50
51DmaPort::DmaPort(MemObject *dev, System *s)
52 : MasterPort(dev->name() + ".dma", dev), device(dev), sendEvent(this),
53 sys(s), masterId(s->getMasterId(dev->name())),
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46#include "debug/DMA.hh"
47#include "debug/Drain.hh"
48#include "dev/dma_device.hh"
49#include "sim/system.hh"
50
51DmaPort::DmaPort(MemObject *dev, System *s)
52 : MasterPort(dev->name() + ".dma", dev), device(dev), sendEvent(this),
53 sys(s), masterId(s->getMasterId(dev->name())),
54 pendingCount(0), drainManager(NULL),
55 inRetry(false)
54 pendingCount(0), inRetry(false)
56{ }
57
58void
59DmaPort::handleResp(PacketPtr pkt, Tick delay)
60{
61 // should always see a response with a sender state
62 assert(pkt->isResponse());
63

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90 delete state;
91 }
92
93 // delete the request that we created and also the packet
94 delete pkt->req;
95 delete pkt;
96
97 // we might be drained at this point, if so signal the drain event
55{ }
56
57void
58DmaPort::handleResp(PacketPtr pkt, Tick delay)
59{
60 // should always see a response with a sender state
61 assert(pkt->isResponse());
62

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89 delete state;
90 }
91
92 // delete the request that we created and also the packet
93 delete pkt->req;
94 delete pkt;
95
96 // we might be drained at this point, if so signal the drain event
98 if (pendingCount == 0 && drainManager) {
99 drainManager->signalDrainDone();
100 drainManager = NULL;
101 }
97 if (pendingCount == 0)
98 signalDrainDone();
102}
103
104bool
105DmaPort::recvTimingResp(PacketPtr pkt)
106{
107 // We shouldn't ever get a cacheable block in ownership state
108 assert(pkt->req->isUncacheable() ||
109 !(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));

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120void
121DmaDevice::init()
122{
123 if (!dmaPort.isConnected())
124 panic("DMA port of %s not connected to anything!", name());
125 PioDevice::init();
126}
127
99}
100
101bool
102DmaPort::recvTimingResp(PacketPtr pkt)
103{
104 // We shouldn't ever get a cacheable block in ownership state
105 assert(pkt->req->isUncacheable() ||
106 !(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));

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117void
118DmaDevice::init()
119{
120 if (!dmaPort.isConnected())
121 panic("DMA port of %s not connected to anything!", name());
122 PioDevice::init();
123}
124
128unsigned int
129DmaPort::drain(DrainManager *dm)
125DrainState
126DmaPort::drain()
130{
127{
131 if (pendingCount == 0)
132 return 0;
133 drainManager = dm;
134 DPRINTF(Drain, "DmaPort not drained\n");
135 return 1;
128 if (pendingCount == 0) {
129 return DrainState::Drained;
130 } else {
131 DPRINTF(Drain, "DmaPort not drained\n");
132 return DrainState::Draining;
133 }
136}
137
138void
139DmaPort::recvReqRetry()
140{
141 assert(transmitList.size());
142 trySendTimingReq();
143}

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135
136void
137DmaPort::recvReqRetry()
138{
139 assert(transmitList.size());
140 trySendTimingReq();
141}

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