dma_device.cc (10024:fc10e1f9f124) dma_device.cc (10621:b7bc5b1084a4)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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147
148void
149DmaPort::recvRetry()
150{
151 assert(transmitList.size());
152 trySendTimingReq();
153}
154
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 138 unchanged lines hidden (view full) ---

147
148void
149DmaPort::recvRetry()
150{
151 assert(transmitList.size());
152 trySendTimingReq();
153}
154
155void
155RequestPtr
156DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
157 uint8_t *data, Tick delay, Request::Flags flag)
158{
159 // one DMA request sender state for every action, that is then
160 // split into many requests and packets based on the block size,
161 // i.e. cache line size
162 DmaReqState *reqState = new DmaReqState(event, size, delay);
163
156DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
157 uint8_t *data, Tick delay, Request::Flags flag)
158{
159 // one DMA request sender state for every action, that is then
160 // split into many requests and packets based on the block size,
161 // i.e. cache line size
162 DmaReqState *reqState = new DmaReqState(event, size, delay);
163
164 // (functionality added for Table Walker statistics)
165 // We're only interested in this when there will only be one request.
166 // For simplicity, we return the last request, which would also be
167 // the only request in that case.
168 RequestPtr req = NULL;
169
164 DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size,
165 event ? event->scheduled() : -1);
166 for (ChunkGenerator gen(addr, size, sys->cacheLineSize());
167 !gen.done(); gen.next()) {
170 DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size,
171 event ? event->scheduled() : -1);
172 for (ChunkGenerator gen(addr, size, sys->cacheLineSize());
173 !gen.done(); gen.next()) {
168 Request *req = new Request(gen.addr(), gen.size(), flag, masterId);
174 req = new Request(gen.addr(), gen.size(), flag, masterId);
169 req->taskId(ContextSwitchTaskId::DMA);
170 PacketPtr pkt = new Packet(req, cmd);
171
172 // Increment the data pointer on a write
173 if (data)
174 pkt->dataStatic(data + gen.complete());
175
176 pkt->senderState = reqState;
177
178 DPRINTF(DMA, "--Queuing DMA for addr: %#x size: %d\n", gen.addr(),
179 gen.size());
180 queueDma(pkt);
181 }
182
183 // in zero time also initiate the sending of the packets we have
184 // just created, for atomic this involves actually completing all
185 // the requests
186 sendDma();
175 req->taskId(ContextSwitchTaskId::DMA);
176 PacketPtr pkt = new Packet(req, cmd);
177
178 // Increment the data pointer on a write
179 if (data)
180 pkt->dataStatic(data + gen.complete());
181
182 pkt->senderState = reqState;
183
184 DPRINTF(DMA, "--Queuing DMA for addr: %#x size: %d\n", gen.addr(),
185 gen.size());
186 queueDma(pkt);
187 }
188
189 // in zero time also initiate the sending of the packets we have
190 // just created, for atomic this involves actually completing all
191 // the requests
192 sendDma();
193
194 return req;
187}
188
189void
190DmaPort::queueDma(PacketPtr pkt)
191{
192 transmitList.push_back(pkt);
193
194 // remember that we have another packet pending, this will only be

--- 74 unchanged lines hidden --- 		195}
196
197void
198DmaPort::queueDma(PacketPtr pkt)
199{
200 transmitList.push_back(pkt);
201
202 // remember that we have another packet pending, this will only be

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