vgic.hh (10037:5cac77888310) vgic.hh (10905:a6ca6831e775)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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47 * The mode in which the List Registers may flag (via LR.HW) that a hardware EOI
48 * is to be performed is NOT supported. (This requires tighter integration with
49 * the GIC.)
50 */
51
52#ifndef __DEV_ARM_VGIC_H__
53#define __DEV_ARM_VGIC_H__
54
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 38 unchanged lines hidden (view full) ---

47 * The mode in which the List Registers may flag (via LR.HW) that a hardware EOI
48 * is to be performed is NOT supported. (This requires tighter integration with
49 * the GIC.)
50 */
51
52#ifndef __DEV_ARM_VGIC_H__
53#define __DEV_ARM_VGIC_H__
54
55#include <algorithm>
56#include <array>
57
55#include "base/addr_range.hh"
56#include "base/bitunion.hh"
57#include "cpu/intr_control.hh"
58#include "dev/io_device.hh"
59#include "dev/platform.hh"
60#include "params/VGic.hh"
61
62class VGic : public PioDevice

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157 Bitfield<2> AckCtl;
158 Bitfield<1> EnGrp1;
159 Bitfield<0> En; // This gets written to enable, not group 1.
160 EndBitUnion(VCTLR)
161
162 /* State per CPU. EVERYTHING should be in this struct and simply replicated
163 * N times.
164 */
58#include "base/addr_range.hh"
59#include "base/bitunion.hh"
60#include "cpu/intr_control.hh"
61#include "dev/io_device.hh"
62#include "dev/platform.hh"
63#include "params/VGic.hh"
64
65class VGic : public PioDevice

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160 Bitfield<2> AckCtl;
161 Bitfield<1> EnGrp1;
162 Bitfield<0> En; // This gets written to enable, not group 1.
163 EndBitUnion(VCTLR)
164
165 /* State per CPU. EVERYTHING should be in this struct and simply replicated
166 * N times.
167 */
165 struct vcpuIntData {
166 ListReg LR[NUM_LR];
168 struct vcpuIntData : public Serializable {
169 vcpuIntData()
170 : vctrl(0), hcr(0), eisr(0), VMGrp0En(0), VMGrp1En(0),
171 VMAckCtl(0), VMFiqEn(0), VMCBPR(0), VEM(0), VMABP(0), VMBP(0),
172 VMPriMask(0)
173 {
174 std::fill(LR.begin(), LR.end(), 0);
175 }
176 virtual ~vcpuIntData() {}
177
178 std::array<ListReg, NUM_LR> LR;
167 VCTLR vctrl;
168
169 HCR hcr;
170 uint64_t eisr;
171
172 /* Host info, guest info (should be 100% accessible via GICH_* regs!) */
173 uint8_t VMGrp0En;
174 uint8_t VMGrp1En;
175 uint8_t VMAckCtl;
176 uint8_t VMFiqEn;
177 uint8_t VMCBPR;
178 uint8_t VEM;
179 uint8_t VMABP;
180 uint8_t VMBP;
181 uint8_t VMPriMask;
179 VCTLR vctrl;
180
181 HCR hcr;
182 uint64_t eisr;
183
184 /* Host info, guest info (should be 100% accessible via GICH_* regs!) */
185 uint8_t VMGrp0En;
186 uint8_t VMGrp1En;
187 uint8_t VMAckCtl;
188 uint8_t VMFiqEn;
189 uint8_t VMCBPR;
190 uint8_t VEM;
191 uint8_t VMABP;
192 uint8_t VMBP;
193 uint8_t VMPriMask;
194
195 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
196 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
182 };
183
197 };
198
184 struct vcpuIntData vcpuData[VGIC_CPU_MAX];
199 struct std::array<vcpuIntData, VGIC_CPU_MAX> vcpuData;
185
186 public:
187 typedef VGicParams Params;
188 const Params *
189 params() const
190 {
191 return dynamic_cast<const Params *>(_params);
192 }
193 VGic(const Params *p);
194
195 virtual AddrRangeList getAddrRanges() const;
196
197 virtual Tick read(PacketPtr pkt);
198 virtual Tick write(PacketPtr pkt);
199
200
201 public:
202 typedef VGicParams Params;
203 const Params *
204 params() const
205 {
206 return dynamic_cast<const Params *>(_params);
207 }
208 VGic(const Params *p);
209
210 virtual AddrRangeList getAddrRanges() const;
211
212 virtual Tick read(PacketPtr pkt);
213 virtual Tick write(PacketPtr pkt);
214
200 virtual void serialize(std::ostream &os);
201 virtual void unserialize(Checkpoint *cp, const std::string &section);
215 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
216 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
202
203 private:
204 Tick readVCpu(PacketPtr pkt);
205 Tick readCtrl(PacketPtr pkt);
206
207 Tick writeVCpu(PacketPtr pkt);
208 Tick writeCtrl(PacketPtr pkt);
209

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218 private:
219 Tick readVCpu(PacketPtr pkt);
220 Tick readCtrl(PacketPtr pkt);
221
222 Tick writeVCpu(PacketPtr pkt);
223 Tick writeCtrl(PacketPtr pkt);
224

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