vgic.cc (10905:a6ca6831e775) vgic.cc (11005:e7f403b6b76f)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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85 panic("Write to unknown address %#x\n", pkt->getAddr());
86}
87
88Tick
89VGic::readVCpu(PacketPtr pkt)
90{
91 Addr daddr = pkt->getAddr() - vcpuAddr;
92
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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85 panic("Write to unknown address %#x\n", pkt->getAddr());
86}
87
88Tick
89VGic::readVCpu(PacketPtr pkt)
90{
91 Addr daddr = pkt->getAddr() - vcpuAddr;
92
93 int ctx_id = pkt->req->contextId();
93 ContextID ctx_id = pkt->req->contextId();
94 assert(ctx_id < VGIC_CPU_MAX);
95 struct vcpuIntData *vid = &vcpuData[ctx_id];
96
97 DPRINTF(VGIC, "VGIC VCPU read register %#x\n", daddr);
98
99 switch (daddr) {
100 case GICV_CTLR:
101 pkt->set<uint32_t>(vid->vctrl);

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129 return pioDelay;
130}
131
132Tick
133VGic::readCtrl(PacketPtr pkt)
134{
135 Addr daddr = pkt->getAddr() - hvAddr;
136
94 assert(ctx_id < VGIC_CPU_MAX);
95 struct vcpuIntData *vid = &vcpuData[ctx_id];
96
97 DPRINTF(VGIC, "VGIC VCPU read register %#x\n", daddr);
98
99 switch (daddr) {
100 case GICV_CTLR:
101 pkt->set<uint32_t>(vid->vctrl);

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129 return pioDelay;
130}
131
132Tick
133VGic::readCtrl(PacketPtr pkt)
134{
135 Addr daddr = pkt->getAddr() - hvAddr;
136
137 int ctx_id = pkt->req->contextId();
137 ContextID ctx_id = pkt->req->contextId();
138
139 DPRINTF(VGIC, "VGIC HVCtrl read register %#x\n", daddr);
140
141 /* Munge the address: 0-0xfff is the usual space banked by requester CPU.
142 * Anything > that is 0x200-sized slices of 'per CPU' regs.
143 */
144 if (daddr & ~0x1ff) {
145 ctx_id = (daddr >> 9);

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223 return pioDelay;
224}
225
226Tick
227VGic::writeVCpu(PacketPtr pkt)
228{
229 Addr daddr = pkt->getAddr() - vcpuAddr;
230
138
139 DPRINTF(VGIC, "VGIC HVCtrl read register %#x\n", daddr);
140
141 /* Munge the address: 0-0xfff is the usual space banked by requester CPU.
142 * Anything > that is 0x200-sized slices of 'per CPU' regs.
143 */
144 if (daddr & ~0x1ff) {
145 ctx_id = (daddr >> 9);

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223 return pioDelay;
224}
225
226Tick
227VGic::writeVCpu(PacketPtr pkt)
228{
229 Addr daddr = pkt->getAddr() - vcpuAddr;
230
231 int ctx_id = pkt->req->contextId();
231 ContextID ctx_id = pkt->req->contextId();
232 assert(ctx_id < VGIC_CPU_MAX);
233 struct vcpuIntData *vid = &vcpuData[ctx_id];
234
235 DPRINTF(VGIC, "VGIC VCPU write register %#x <= %#x\n", daddr, pkt->get<uint32_t>());
236
237 switch (daddr) {
238 case GICV_CTLR:
239 vid->vctrl = pkt->get<uint32_t>();

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270 return pioDelay;
271}
272
273Tick
274VGic::writeCtrl(PacketPtr pkt)
275{
276 Addr daddr = pkt->getAddr() - hvAddr;
277
232 assert(ctx_id < VGIC_CPU_MAX);
233 struct vcpuIntData *vid = &vcpuData[ctx_id];
234
235 DPRINTF(VGIC, "VGIC VCPU write register %#x <= %#x\n", daddr, pkt->get<uint32_t>());
236
237 switch (daddr) {
238 case GICV_CTLR:
239 vid->vctrl = pkt->get<uint32_t>();

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270 return pioDelay;
271}
272
273Tick
274VGic::writeCtrl(PacketPtr pkt)
275{
276 Addr daddr = pkt->getAddr() - hvAddr;
277
278 int ctx_id = pkt->req->contextId();
278 ContextID ctx_id = pkt->req->contextId();
279
280 DPRINTF(VGIC, "VGIC HVCtrl write register %#x <= %#x\n", daddr, pkt->get<uint32_t>());
281
282 /* Munge the address: 0-0xfff is the usual space banked by requester CPU.
283 * Anything > that is 0x200-sized slices of 'per CPU' regs.
284 */
285 if (daddr & ~0x1ff) {
286 ctx_id = (daddr >> 9);

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375 DPRINTF(VGIC, "Unposting maintenance PPI to GIC/cpu%d\n", cpu);
376 gic->clearPPInt(maintInt, cpu);
377}
378
379/* Update state (in general); something concerned with ctx_id has changed.
380 * This may raise a maintenance interrupt.
381 */
382void
279
280 DPRINTF(VGIC, "VGIC HVCtrl write register %#x <= %#x\n", daddr, pkt->get<uint32_t>());
281
282 /* Munge the address: 0-0xfff is the usual space banked by requester CPU.
283 * Anything > that is 0x200-sized slices of 'per CPU' regs.
284 */
285 if (daddr & ~0x1ff) {
286 ctx_id = (daddr >> 9);

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375 DPRINTF(VGIC, "Unposting maintenance PPI to GIC/cpu%d\n", cpu);
376 gic->clearPPInt(maintInt, cpu);
377}
378
379/* Update state (in general); something concerned with ctx_id has changed.
380 * This may raise a maintenance interrupt.
381 */
382void
383VGic::updateIntState(int ctx_id)
383VGic::updateIntState(ContextID ctx_id)
384{
385 // @todo This should update APRs!
386
387 // Build EISR contents:
388 // (Cached so that regs can read them without messing about again)
389 struct vcpuIntData *tvid = &vcpuData[ctx_id];
390
391 tvid->eisr = 0;

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385 // @todo This should update APRs!
386
387 // Build EISR contents:
388 // (Cached so that regs can read them without messing about again)
389 struct vcpuIntData *tvid = &vcpuData[ctx_id];
390
391 tvid->eisr = 0;

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