vgic.cc (10037:5cac77888310) vgic.cc (10565:23593fdaadcd)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 78 unchanged lines hidden (view full) ---

87 else
88 panic("Write to unknown address %#x\n", pkt->getAddr());
89}
90
91Tick
92VGic::readVCpu(PacketPtr pkt)
93{
94 Addr daddr = pkt->getAddr() - vcpuAddr;
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 78 unchanged lines hidden (view full) ---

87 else
88 panic("Write to unknown address %#x\n", pkt->getAddr());
89}
90
91Tick
92VGic::readVCpu(PacketPtr pkt)
93{
94 Addr daddr = pkt->getAddr() - vcpuAddr;
95 pkt->allocate();
96
97 int ctx_id = pkt->req->contextId();
98 assert(ctx_id < VGIC_CPU_MAX);
99 struct vcpuIntData *vid = &vcpuData[ctx_id];
100
101 DPRINTF(VGIC, "VGIC VCPU read register %#x\n", daddr);
102
103 switch (daddr) {

--- 28 unchanged lines hidden (view full) ---

132 pkt->makeAtomicResponse();
133 return pioDelay;
134}
135
136Tick
137VGic::readCtrl(PacketPtr pkt)
138{
139 Addr daddr = pkt->getAddr() - hvAddr;
95
96 int ctx_id = pkt->req->contextId();
97 assert(ctx_id < VGIC_CPU_MAX);
98 struct vcpuIntData *vid = &vcpuData[ctx_id];
99
100 DPRINTF(VGIC, "VGIC VCPU read register %#x\n", daddr);
101
102 switch (daddr) {

--- 28 unchanged lines hidden (view full) ---

131 pkt->makeAtomicResponse();
132 return pioDelay;
133}
134
135Tick
136VGic::readCtrl(PacketPtr pkt)
137{
138 Addr daddr = pkt->getAddr() - hvAddr;
140 pkt->allocate();
141
142 int ctx_id = pkt->req->contextId();
143
144 DPRINTF(VGIC, "VGIC HVCtrl read register %#x\n", daddr);
145
146 /* Munge the address: 0-0xfff is the usual space banked by requester CPU.
147 * Anything > that is 0x200-sized slices of 'per CPU' regs.
148 */

--- 78 unchanged lines hidden (view full) ---

227 pkt->makeAtomicResponse();
228 return pioDelay;
229}
230
231Tick
232VGic::writeVCpu(PacketPtr pkt)
233{
234 Addr daddr = pkt->getAddr() - vcpuAddr;
139
140 int ctx_id = pkt->req->contextId();
141
142 DPRINTF(VGIC, "VGIC HVCtrl read register %#x\n", daddr);
143
144 /* Munge the address: 0-0xfff is the usual space banked by requester CPU.
145 * Anything > that is 0x200-sized slices of 'per CPU' regs.
146 */

--- 78 unchanged lines hidden (view full) ---

225 pkt->makeAtomicResponse();
226 return pioDelay;
227}
228
229Tick
230VGic::writeVCpu(PacketPtr pkt)
231{
232 Addr daddr = pkt->getAddr() - vcpuAddr;
235 pkt->allocate();
236
237 int ctx_id = pkt->req->contextId();
238 assert(ctx_id < VGIC_CPU_MAX);
239 struct vcpuIntData *vid = &vcpuData[ctx_id];
240
241 DPRINTF(VGIC, "VGIC VCPU write register %#x <= %#x\n", daddr, pkt->get<uint32_t>());
242
243 switch (daddr) {

--- 31 unchanged lines hidden (view full) ---

275 pkt->makeAtomicResponse();
276 return pioDelay;
277}
278
279Tick
280VGic::writeCtrl(PacketPtr pkt)
281{
282 Addr daddr = pkt->getAddr() - hvAddr;
233
234 int ctx_id = pkt->req->contextId();
235 assert(ctx_id < VGIC_CPU_MAX);
236 struct vcpuIntData *vid = &vcpuData[ctx_id];
237
238 DPRINTF(VGIC, "VGIC VCPU write register %#x <= %#x\n", daddr, pkt->get<uint32_t>());
239
240 switch (daddr) {

--- 31 unchanged lines hidden (view full) ---

272 pkt->makeAtomicResponse();
273 return pioDelay;
274}
275
276Tick
277VGic::writeCtrl(PacketPtr pkt)
278{
279 Addr daddr = pkt->getAddr() - hvAddr;
283 pkt->allocate();
284
285 int ctx_id = pkt->req->contextId();
286
287 DPRINTF(VGIC, "VGIC HVCtrl write register %#x <= %#x\n", daddr, pkt->get<uint32_t>());
288
289 /* Munge the address: 0-0xfff is the usual space banked by requester CPU.
290 * Anything > that is 0x200-sized slices of 'per CPU' regs.
291 */

--- 262 unchanged lines hidden --- 		280
281 int ctx_id = pkt->req->contextId();
282
283 DPRINTF(VGIC, "VGIC HVCtrl write register %#x <= %#x\n", daddr, pkt->get<uint32_t>());
284
285 /* Munge the address: 0-0xfff is the usual space banked by requester CPU.
286 * Anything > that is 0x200-sized slices of 'per CPU' regs.
287 */

--- 262 unchanged lines hidden ---