1/*
2 * Copyright (c) 2013-2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Rene de Jong
38 */
39
40
41/** @file
42 * This is a base class for UFS devices
43 * The UFS interface consists out of one host controller which connects a
44 * number of devices which together contain up to 8 logic units. A Logical
45 * Unit is an externally addressable, independent, processing entity that
46 * processes SCSI tasks (commands) and performs task management functions.
47 * The decision has been made to abstract the device away, and model the
48 * different logic units. Effectively this means that there is one Host layer
49 * which handles all the UFS commands (everything UTP, UPIU and UNIpro
50 * related) and a SCSI layer, which handles the SCSI interpretation and the
51 * interaction with the "disk" (effectively the LBA that that particular
52 * Logic Unit controls). Each Logic unit should therefor control a disk image
53 * and a timing model. The UFS protocol has three types of commands
54 * (explained later). Each has different phases and each phase need to wait
55 * for its particular data. This is the reason that this model contains a lot
56 * of events. For clarity, a state diagram in doxygen has been provided. To
57 * fully apreciate the stages that the model flows through, the states have
58 * been broken into three state diagrams. It is best if one imagines the
59 * command flow state machine to be happening in the UFSHost layer, and the
60 * other two to flow through all the layers of the model (UFS host, SCSI and
61 * NVM model). See it as a quarry, one state diagram is moving the crane into
62 * place, and the other ones are transporting the dirt down, or the valuables
63 * up. For complete information about the working of UFS please refer to
64 * http://www.jedec.org/standards-documents/results/jesd220 or
65 * http://www.jedec.org/standards-documents/results/jesd223
66 * The documents are available free of charge, although you will need to have
67 * an acount.
68 */
69
70/** UFS command flow state machine
71 *digraph CommandFlow{
72 node [fontsize=10];
73 IDLE -> transferHandler
74 [ label=" transfer/task/command request " fontsize=6];
75 transferHandler -> command
76 [ label=" It is a command " fontsize=6];
77 command -> IDLE
78 [ label=" Command done, no further action " fontsize=6];
79 transferHandler -> taskStart
80 [ label=" It is a task " fontsize=6];
81 taskStart -> finalUTP
82 [ label=" Task handled, now acknowledge (UFS) " fontsize=6];
83 transferHandler -> transferStart
84 [ label=" It is a transfer " fontsize=6];
85 transferStart -> SCSIResume
86 [ label=" Transfer, obtain the specific command " fontsize=6];
87 SCSIResume -> DiskDataFlowPhase
88 [ label=" Disk data transfer (see other graphs) " fontsize=6];
89 SCSIResume -> DeviceDataPhase
90 [ label=" Device info transfer (handled in SCSIResume) "
91 fontsize=6];
92 DiskDataFlowPhase -> transferDone
93 [ label=" Transfer done, acknowledge SCSI command " fontsize=6];
94 DeviceDataPhase -> transferDone
95 [ label=" Transfer done, acknowledge SCSI command " fontsize=6];
96 transferDone -> finalUTP
97 [ label=" Transfer handled, now acknowledge (UFS) " fontsize=6];
98 finalUTP -> readDone
99 [ label=" All handled, clear data structures " fontsize=6];
100 readDone -> IDLE
101 [ label=" All handled, nothing outstanding " fontsize=6];
102 readDone -> transferHandler
103 [ label=" All handled, handle next outstanding " fontsize=6];
104 }
105 */
106/** UFS read transaction flow state machine
107 digraph readFlow{
108 node [fontsize=10];
109 getScatterGather -> commitReadFromDisk
110 [ label=" Put the information about the data transfer to the disk "
111 fontsize=6];
112 commitReadFromDisk -> waitForReads
113 [ label=" Push the reads to the flashmodel and wait for callbacks "
114 fontsize=6];
115 waitForReads -> pushToDMA
116 [ label=" Push to the DMA and wait for them to finish " fontsize=6];
117 pushToDMA -> waitForReads
118 [ label=" Wait for the next disk event " fontsize=6];
119 pushToDMA -> waitForDMA
120 [ label=" Wait for the last DMA transfer to finish " fontsize=6];
121 waitForDMA -> finishTransfer
122 [ label=" Continue with the command flow " fontsize=6];
123 }
124 */
125/** UFS write transaction flow state machine
126 digraph WriteFlow{
127 node [fontsize=10];
128 getScatterGather -> getFromDMA
129 [ label=" Put the transfer information to the DMA " fontsize=6];
130 getFromDMA -> waitForDMA
131 [ label=" Wait for dma actions to arrive " fontsize=6];
132 waitForDMA -> pushToDisk
133 [ label=" Push arrived DMA to disk " fontsize=6];
134 pushToDisk -> waitForDMA
135 [ label=" Wait for next DMA action " fontsize=6];
136 pushToDisk -> waitForDisk
137 [ label=" All DMA actions are done, wait for disk " fontsize=6];
138 waitForDisk -> finishTransfer
139 [ label=" All transactions are done , continue the command flow "
140 fontsize=6];
141 }
142 */
143
144#ifndef __DEV_ARM_UFS_DEVICE_HH__
145#define __DEV_ARM_UFS_DEVICE_HH__
146
147#include <deque>
148
149#include "base/addr_range.hh"
150#include "base/bitfield.hh"
151#include "base/statistics.hh"
152#include "debug/UFSHostDevice.hh"
153#include "dev/arm/abstract_nvm.hh"
154#include "dev/arm/base_gic.hh"
155#include "dev/disk_image.hh"
156#include "dev/dma_device.hh"
157#include "dev/io_device.hh"
158#include "mem/packet.hh"
159#include "mem/packet_access.hh"
160#include "params/UFSHostDevice.hh"
161#include "sim/serialize.hh"
162#include "sim/stats.hh"
163
164/**
165 * Host controller layer: This is your Host controller
166 * This layer handles the UFS functionality.
167 * It tracks all the different transaction stages and uses
168 * the device layer and the flash layer to determine the transaction flow.
169 */
170class UFSHostDevice : public DmaDevice
171{
172 public:
173
174 UFSHostDevice(const UFSHostDeviceParams* p);
175
176 unsigned int drain(DrainManager *dm);
177 void checkDrain();
| 1/*
2 * Copyright (c) 2013-2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Rene de Jong
38 */
39
40
41/** @file
42 * This is a base class for UFS devices
43 * The UFS interface consists out of one host controller which connects a
44 * number of devices which together contain up to 8 logic units. A Logical
45 * Unit is an externally addressable, independent, processing entity that
46 * processes SCSI tasks (commands) and performs task management functions.
47 * The decision has been made to abstract the device away, and model the
48 * different logic units. Effectively this means that there is one Host layer
49 * which handles all the UFS commands (everything UTP, UPIU and UNIpro
50 * related) and a SCSI layer, which handles the SCSI interpretation and the
51 * interaction with the "disk" (effectively the LBA that that particular
52 * Logic Unit controls). Each Logic unit should therefor control a disk image
53 * and a timing model. The UFS protocol has three types of commands
54 * (explained later). Each has different phases and each phase need to wait
55 * for its particular data. This is the reason that this model contains a lot
56 * of events. For clarity, a state diagram in doxygen has been provided. To
57 * fully apreciate the stages that the model flows through, the states have
58 * been broken into three state diagrams. It is best if one imagines the
59 * command flow state machine to be happening in the UFSHost layer, and the
60 * other two to flow through all the layers of the model (UFS host, SCSI and
61 * NVM model). See it as a quarry, one state diagram is moving the crane into
62 * place, and the other ones are transporting the dirt down, or the valuables
63 * up. For complete information about the working of UFS please refer to
64 * http://www.jedec.org/standards-documents/results/jesd220 or
65 * http://www.jedec.org/standards-documents/results/jesd223
66 * The documents are available free of charge, although you will need to have
67 * an acount.
68 */
69
70/** UFS command flow state machine
71 *digraph CommandFlow{
72 node [fontsize=10];
73 IDLE -> transferHandler
74 [ label=" transfer/task/command request " fontsize=6];
75 transferHandler -> command
76 [ label=" It is a command " fontsize=6];
77 command -> IDLE
78 [ label=" Command done, no further action " fontsize=6];
79 transferHandler -> taskStart
80 [ label=" It is a task " fontsize=6];
81 taskStart -> finalUTP
82 [ label=" Task handled, now acknowledge (UFS) " fontsize=6];
83 transferHandler -> transferStart
84 [ label=" It is a transfer " fontsize=6];
85 transferStart -> SCSIResume
86 [ label=" Transfer, obtain the specific command " fontsize=6];
87 SCSIResume -> DiskDataFlowPhase
88 [ label=" Disk data transfer (see other graphs) " fontsize=6];
89 SCSIResume -> DeviceDataPhase
90 [ label=" Device info transfer (handled in SCSIResume) "
91 fontsize=6];
92 DiskDataFlowPhase -> transferDone
93 [ label=" Transfer done, acknowledge SCSI command " fontsize=6];
94 DeviceDataPhase -> transferDone
95 [ label=" Transfer done, acknowledge SCSI command " fontsize=6];
96 transferDone -> finalUTP
97 [ label=" Transfer handled, now acknowledge (UFS) " fontsize=6];
98 finalUTP -> readDone
99 [ label=" All handled, clear data structures " fontsize=6];
100 readDone -> IDLE
101 [ label=" All handled, nothing outstanding " fontsize=6];
102 readDone -> transferHandler
103 [ label=" All handled, handle next outstanding " fontsize=6];
104 }
105 */
106/** UFS read transaction flow state machine
107 digraph readFlow{
108 node [fontsize=10];
109 getScatterGather -> commitReadFromDisk
110 [ label=" Put the information about the data transfer to the disk "
111 fontsize=6];
112 commitReadFromDisk -> waitForReads
113 [ label=" Push the reads to the flashmodel and wait for callbacks "
114 fontsize=6];
115 waitForReads -> pushToDMA
116 [ label=" Push to the DMA and wait for them to finish " fontsize=6];
117 pushToDMA -> waitForReads
118 [ label=" Wait for the next disk event " fontsize=6];
119 pushToDMA -> waitForDMA
120 [ label=" Wait for the last DMA transfer to finish " fontsize=6];
121 waitForDMA -> finishTransfer
122 [ label=" Continue with the command flow " fontsize=6];
123 }
124 */
125/** UFS write transaction flow state machine
126 digraph WriteFlow{
127 node [fontsize=10];
128 getScatterGather -> getFromDMA
129 [ label=" Put the transfer information to the DMA " fontsize=6];
130 getFromDMA -> waitForDMA
131 [ label=" Wait for dma actions to arrive " fontsize=6];
132 waitForDMA -> pushToDisk
133 [ label=" Push arrived DMA to disk " fontsize=6];
134 pushToDisk -> waitForDMA
135 [ label=" Wait for next DMA action " fontsize=6];
136 pushToDisk -> waitForDisk
137 [ label=" All DMA actions are done, wait for disk " fontsize=6];
138 waitForDisk -> finishTransfer
139 [ label=" All transactions are done , continue the command flow "
140 fontsize=6];
141 }
142 */
143
144#ifndef __DEV_ARM_UFS_DEVICE_HH__
145#define __DEV_ARM_UFS_DEVICE_HH__
146
147#include <deque>
148
149#include "base/addr_range.hh"
150#include "base/bitfield.hh"
151#include "base/statistics.hh"
152#include "debug/UFSHostDevice.hh"
153#include "dev/arm/abstract_nvm.hh"
154#include "dev/arm/base_gic.hh"
155#include "dev/disk_image.hh"
156#include "dev/dma_device.hh"
157#include "dev/io_device.hh"
158#include "mem/packet.hh"
159#include "mem/packet_access.hh"
160#include "params/UFSHostDevice.hh"
161#include "sim/serialize.hh"
162#include "sim/stats.hh"
163
164/**
165 * Host controller layer: This is your Host controller
166 * This layer handles the UFS functionality.
167 * It tracks all the different transaction stages and uses
168 * the device layer and the flash layer to determine the transaction flow.
169 */
170class UFSHostDevice : public DmaDevice
171{
172 public:
173
174 UFSHostDevice(const UFSHostDeviceParams* p);
175
176 unsigned int drain(DrainManager *dm);
177 void checkDrain();
|
180
181 private:
182 /**
183 * Host Controller Interface
184 * This is a set of registers that allow the driver to control the
185 * transactions to the flash devices.
186 * As defined in:
187 * http://www.jedec.org/standards-documents/results/jesd223
188 */
189 struct HCIMem {
190 /**
191 * Specify the host capabilities
192 */
193 uint32_t HCCAP;
194 uint32_t HCversion;
195 uint32_t HCHCDDID;
196 uint32_t HCHCPMID;
197
198 /**
199 * Operation and runtime registers
200 */
201 uint32_t ORInterruptStatus;
202 uint32_t ORInterruptEnable;
203 uint32_t ORHostControllerStatus;
204 uint32_t ORHostControllerEnable;
205 uint32_t ORUECPA;
206 uint32_t ORUECDL;
207 uint32_t ORUECN;
208 uint32_t ORUECT;
209 uint32_t ORUECDME;
210 uint32_t ORUTRIACR;
211
212 /**
213 * vendor specific register
214 */
215 uint32_t vendorSpecific;
216
217 /**
218 * Transfer control registers
219 */
220 uint32_t TRUTRLBA;
221 uint32_t TRUTRLBAU;
222 uint32_t TRUTRLDBR;
223 uint32_t TRUTRLCLR;
224 uint32_t TRUTRLRSR;
225
226 /**
227 * Task control registers
228 */
229 uint32_t TMUTMRLBA;
230 uint32_t TMUTMRLBAU;
231 uint32_t TMUTMRLDBR;
232 uint32_t TMUTMRLCLR;
233 uint32_t TMUTMRLRSR;
234
235 /**
236 * Command registers
237 */
238 uint32_t CMDUICCMDR;
239 uint32_t CMDUCMDARG1;
240 uint32_t CMDUCMDARG2;
241 uint32_t CMDUCMDARG3;
242 };
243
244 /**
245 * All the data structures are defined in the UFS standard
246 * This standard be found at the JEDEC website free of charge
247 * (login required):
248 * http://www.jedec.org/standards-documents/results/jesd220
249 */
250
251 /**
252 * struct UTPUPIUHeader - UPIU header structure
253 * dWord0: UPIU header DW-0
254 * dWord1: UPIU header DW-1
255 * dWord2: UPIU header DW-2
256 */
257 struct UTPUPIUHeader {
258 uint32_t dWord0;
259 uint32_t dWord1;
260 uint32_t dWord2;
261 };
262
263 /**
264 * struct UTPUPIURSP - Response UPIU structure
265 * header: UPIU header DW-0 to DW-2
266 * residualTransferCount: Residual transfer count DW-3
267 * reserved: Reserved DW-4 to DW-7
268 * senseDataLen: Sense data length DW-8 U16
269 * senseData: Sense data field DW-8 to DW-12
270 */
271 struct UTPUPIURSP {
272 struct UTPUPIUHeader header;
273 uint32_t residualTransferCount;
274 uint32_t reserved[4];
275 uint16_t senseDataLen;
276 uint8_t senseData[18];
277 };
278
279 /**
280 * struct UTPUPIUTaskReq - Task request UPIU structure
281 * header - UPIU header structure DW0 to DW-2
282 * inputParam1: Input param 1 DW-3
283 * inputParam2: Input param 2 DW-4
284 * inputParam3: Input param 3 DW-5
285 * reserved: Reserver DW-6 to DW-7
286 */
287 struct UTPUPIUTaskReq {
288 struct UTPUPIUHeader header;
289 uint32_t inputParam1;
290 uint32_t inputParam2;
291 uint32_t inputParam3;
292 uint32_t reserved[2];
293 };
294
295 /**
296 * struct UFSHCDSGEntry - UFSHCI PRD Entry
297 * baseAddr: Lower 32bit physical address DW-0
298 * upperAddr: Upper 32bit physical address DW-1
299 * reserved: Reserved for future use DW-2
300 * size: size of physical segment DW-3
301 */
302 struct UFSHCDSGEntry {
303 uint32_t baseAddr;
304 uint32_t upperAddr;
305 uint32_t reserved;
306 uint32_t size;
307 };
308
309 /**
310 * struct UTPTransferCMDDesc - UFS Commad Descriptor structure
311 * commandUPIU: Command UPIU Frame address
312 * responseUPIU: Response UPIU Frame address
313 * PRDTable: Physcial Region Descriptor
314 * All lengths as defined by JEDEC220
315 */
316 struct UTPTransferCMDDesc {
317 uint8_t commandUPIU[128];
318 uint8_t responseUPIU[128];
319 struct UFSHCDSGEntry PRDTable[128];
320 };
321
322 /**
323 * UPIU tranfer message.
324 */
325 struct UPIUMessage {
326 struct UTPUPIUHeader header;
327 uint32_t dataOffset;
328 uint32_t dataCount;
329 std::vector<uint32_t> dataMsg;
330 };
331
332 /**
333 * struct UTPTransferReqDesc - UTRD structure
334 * header: UTRD header DW-0 to DW-3
335 * commandDescBaseAddrLo: UCD base address low DW-4
336 * commandDescBaseAddrHi: UCD base address high DW-5
337 * responseUPIULength: response UPIU length DW-6
338 * responseUPIUOffset: response UPIU offset DW-6
339 * PRDTableLength: Physical region descriptor length DW-7
340 * PRDTableOffset: Physical region descriptor offset DW-7
341 */
342 struct UTPTransferReqDesc {
343
344 /**
345 * struct RequestDescHeader
346 * dword0: Descriptor Header DW0
347 * dword1: Descriptor Header DW1
348 * dword2: Descriptor Header DW2
349 * dword3: Descriptor Header DW3
350 */
351 struct RequestDescHeader {
352 uint32_t dWord0;
353 uint32_t dWord1;
354 uint32_t dWord2;
355 uint32_t dWord3;
356 } header;
357
358 /* DW 4-5*/
359 uint32_t commandDescBaseAddrLo;
360 uint32_t commandDescBaseAddrHi;
361
362 /* DW 6 */
363 uint16_t responseUPIULength;
364 uint16_t responseUPIUOffset;
365
366 /* DW 7 */
367 uint16_t PRDTableLength;
368 uint16_t PRDTableOffset;
369 };
370
371 /**
372 * SCSI reply structure. In here is all the information that is needed to
373 * build a SCSI reply.
374 */
375 struct SCSIReply {
376 uint8_t status;
377 uint32_t msgSize;
378 uint8_t LUN;
379 struct UPIUMessage message;
380 uint8_t senseSize;
381 uint8_t expectMore;//0x01 is for writes, 0x02 is for reads
382 uint64_t offset;
383 uint8_t senseCode[19];
384 };
385
386 /**
387 * Logic unit information structure. SCSI requires information of each LUN.
388 * This structure is defined in the SCSI standard, and can also be found in
389 * the UFS standard. http://www.jedec.org/standards-documents/results/jesd220
390 */
391 struct LUNInfo {
392 uint32_t dWord0;
393 uint32_t dWord1;
394 uint32_t vendor0;
395 uint32_t vendor1;
396 uint32_t product0;
397 uint32_t product1;
398 uint32_t product2;
399 uint32_t product3;
400 uint32_t productRevision;
401 };
402
403 /**
404 * Different events, and scenarios require different types of information.
405 * Keep in mind that for a read-from-disk transaction the host at first a
406 * datastructure fetches to determine where and what the command is, then the
407 * command fetches and the structure fetches to determine where the
408 * different read transactions should be placed and then transfers all the
409 * read fragments. It then answers to the original caller with two replies,
410 * one for the command, and one for UFS. Each of these stages trigger a
411 * different event, and each event needs to know what happened in the
412 * previous stage and what is going to happen in the current one. This
413 * happens also for writes, SCSI maintanance, UFS maintanance, command
414 * management and task management.
415 */
416
417 /**
418 * Transfer information.
419 * @filePointer this does not point to a file, but to a position on the disk
420 * image (which is from the software systems perspective a position in a file)
421 */
422 struct transferInfo {
423 std::vector <uint8_t> buffer;
424 uint32_t size;
425 uint64_t offset;
426 uint32_t filePointer;
427 uint32_t lunID;
428 };
429
430 /**
431 * transfer completion info.
432 * This information is needed by transferDone to finish the transfer.
433 */
434 struct transferDoneInfo {
435 Addr responseStartAddr;
436 uint32_t reqPos;
437 struct UTPUPIURSP requestOut;
438 uint32_t size;
439 Addr address;
440 uint8_t *destination;
441 bool finished;
442 uint32_t lunID;
443 };
444
445 /**
446 * Transfer start information.
447 */
448 struct transferStart {
449 struct UTPTransferReqDesc* destination;
450 uint32_t mask;
451 Addr address;
452 uint32_t size;
453 uint32_t done;
454 uint32_t lun_id;
455 };
456
457 /**
458 * Task start information. This is for the device, so no lun id needed.
459 */
460 struct taskStart {
461 struct UTPUPIUTaskReq destination;
462 uint32_t mask;
463 Addr address;
464 uint32_t size;
465 bool done;
466 };
467
468 /**
469 * After a SCSI command has been identified, the SCSI resume function will
470 * handle it. This information will provide context information.
471 */
472 struct SCSIResumeInfo {
473 struct UTPTransferReqDesc* RequestIn;
474 int reqPos;
475 Addr finalAddress;
476 uint32_t finalSize;
477 std::vector <uint8_t> destination;
478 uint32_t done;
479 };
480
481 /**
482 * Disk transfer burst information. Needed to allow communication between the
483 * disk transactions and dma transactions.
484 */
485 struct writeToDiskBurst {
486 Addr start;
487 uint64_t SCSIDiskOffset;
488 uint32_t size;
489 uint32_t LUN;
490 };
491
492 /**
493 * Statistics
494 */
495 struct UFSHostDeviceStats {
496 /** Queue lengths */
497 Stats::Scalar currentSCSIQueue;
498 Stats::Scalar currentReadSSDQueue;
499 Stats::Scalar currentWriteSSDQueue;
500
501 /** Amount of data read/written */
502 Stats::Scalar totalReadSSD;
503 Stats::Scalar totalWrittenSSD;
504 Stats::Scalar totalReadDiskTransactions;
505 Stats::Scalar totalWriteDiskTransactions;
506 Stats::Scalar totalReadUFSTransactions;
507 Stats::Scalar totalWriteUFSTransactions;
508
509 /** Average bandwidth for reads and writes */
510 Stats::Formula averageReadSSDBW;
511 Stats::Formula averageWriteSSDBW;
512
513 /** Average Queue lengths*/
514 Stats::Average averageSCSIQueue;
515 Stats::Average averageReadSSDQueue;
516 Stats::Average averageWriteSSDQueue;
517
518 /** Number of doorbells rung*/
519 Stats::Formula curDoorbell;
520 Stats::Scalar maxDoorbell;
521 Stats::Average averageDoorbell;
522
523 /** Histogram of latencies*/
524 Stats::Histogram transactionLatency;
525 Stats::Histogram idleTimes;
526 };
527
528 /**
529 * device layer: This is your Logic unit
530 * This layer implements the SCSI functionality of the UFS Device
531 * One logic unit controls one or more disk partitions
532 */
533 class UFSSCSIDevice: SimObject
534 {
535 public:
536 /**
537 * Constructor and destructor
538 */
539 UFSSCSIDevice(const UFSHostDeviceParams* p, uint32_t lun_id, Callback*
540 transfer_cb, Callback *read_cb);
541 ~UFSSCSIDevice();
542
543 /**
544 * SCSI command handle function; determines what the command is and
545 * returns a reply structure that allows the host device to continue
546 * with the transfer.
547 */
548 struct SCSIReply SCSICMDHandle(uint32_t* SCSI_msg);
549
550 /**
551 * Disk access functions. These will transfer the data from/to the disk
552 */
553
554 /**
555 * Read flash. read the data from the disk image. This function
556 * doesn't model timing behaviour
557 */
558 void readFlash(uint8_t* readaddr, uint64_t offset, uint32_t size);
559
560 /**
561 * Write flash. write the data to the disk image. This function
562 * doesn't model timing behaviour
563 */
564 void writeFlash(uint8_t* writeaddr, uint64_t offset, uint32_t size);
565
566 /**
567 * finished command. Probe to find out wether this logic unit
568 * finished its transfer and triggered the callback; The host needs
569 * this to handle the final part of the transaction.
570 */
571 bool finishedCommand() const {return transferCompleted;};
572
573 /**
574 * Clear signal. Handle for the host to clear the transfer complete
575 * signal.
576 */
577 void clearSignal() {transferCompleted = false;};
578
579 /**
580 * Finished read. Probe to find out which logic unit finished its
581 * read. This is needed, because multiple units can do transactions
582 * at the same time, and need to push back data at the right time in
583 * the right order. (because writes work the other way round, they do
584 * not need this mechanism)
585 */
586 bool finishedRead() const {return readCompleted;};
587
588 /**
589 * Clear signal. Handle for the host to clear the read complete
590 * signal.
591 */
592 void clearReadSignal() {readCompleted = false;};
593
594 /**
595 * Start the transactions to (and from) the disk
596 * The host will queue all the transactions. Once the next phase
597 * commences, this function should be started.
598 */
599 void SSDReadStart(uint32_t total_read);
600 void SSDWriteStart();
601
602 /**
603 * Sets total amount of write transactions that needs to be made.
604 * First they need to be fetched via DMA, so this value is needed in
605 * a later stage.
606 */
607 void setTotalWrite(uint32_t total_write) {totalWrite = total_write;};
608
609 /**
610 * End of transfer information
611 */
612 transferDoneInfo transferInfo;
613
614 /**
615 * Information message queues, as there can be multiple messages
616 * queued for handling in this system. These are the main
617 * communication interfaces between the Host and the device layers
618 */
619
620 /**
621 * SCSIInfoQueue: each LU handles its own SCSI commands.
622 */
623 std::deque<struct SCSIResumeInfo> SCSIInfoQueue;
624
625 /**
626 * SSDReadInfo: Structure from disk to dma, that contains data, and
627 * helper info to get it to the right place in the memory.
628 */
629 std::deque<struct transferInfo> SSDReadInfo;
630
631 /**
632 * SSDWriteDoneInfo: Structure from dma to disk, that contains data,
633 * and helper info to get it to the right place in the memory.
634 * The done is added because it is going to the last phase of the
635 * write transfer.
636 */
637 std::deque<struct transferInfo> SSDWriteDoneInfo;
638
639 private:
640 /**
641 * Functions to indicate that the action to the SSD has completed.
642 */
643 /**
644 * Read Call back; This is the callback function for the memory model
645 */
646 void readCallback();
647
648 /**
649 * SSD Read done; Determines if the final callback of the transaction
650 * should be made at the end of a read transfer.
651 */
652 void SSDReadDone();
653
654 /**
655 * SSD Write Done; This is the callback function for the memory model.
656 */
657 void SSDWriteDone();
658
659 /**
660 * Status of SCSI. This may be linked to a status check in the future.
661 * For now it (mainly) fills a data structure with sense information
662 * for a successfull transaction
663 */
664 void statusCheck(uint8_t status, uint8_t* sensecodelist);
665
666 /**
667 * set signal to indicate that the transaction has been completed.
668 */
669 void setSignal() {transferCompleted = true;};
670
671 /**
672 * set signal to indicate that the read action has been completed
673 */
674 void setReadSignal() {readCompleted = true;};
675
676 /**
677 * The objects this model links to.
678 * 1: the disk data model
679 * 2: the memory timing model
680 */
681 DiskImage* flashDisk;
682 AbstractNVM* flashDevice;
683
684 /**
685 * Logic unit dimensions
686 */
687 const uint32_t blkSize;
688 const uint32_t lunAvail;
689 const uint64_t diskSize;
690 const uint32_t capacityLower;
691 const uint32_t capacityUpper;
692
693 /**
694 * Logic unit info; needed for SCSI Info messages and LU
695 * identification
696 */
697 struct LUNInfo lunInfo;
698 const uint32_t lunID;
699
700 /**
701 * Signals to Host layer
702 * 1: signal for transaction completion
703 * 2: signal for read action completion
704 */
705 bool transferCompleted;
706 bool readCompleted;
707
708 /**
709 * Total amount transactions that need to be made
710 */
711 uint32_t totalRead;
712 uint32_t totalWrite;
713
714 /**
715 * transaction progress tracking
716 */
717 uint32_t amountOfWriteTransfers;
718 uint32_t amountOfReadTransfers;
719
720 /**
721 * Callbacks between Host and Device
722 */
723 Callback* signalDone;
724 Callback* deviceReadCallback;
725
726 /**
727 * Callbacks between Device and Memory
728 */
729 Callback* memReadCallback;
730 Callback* memWriteCallback;
731
732 /*
733 * Default response header layout. For more information refer to
734 * chapter 7 http://www.jedec.org/standards-documents/results/jesd220
735 */
736 static const unsigned int UPIUHeaderDataIndWord0 = 0x0000C022;
737 static const unsigned int UPIUHeaderDataIndWord1 = 0x00000000;
738 static const unsigned int UPIUHeaderDataIndWord2 = 0x40000000;
739
740 /*
741 * SCSI mode pages values assigned in ufs_device.cc
742 * The mode pages give device specific information via the SCSI
743 * protocol. They are defined in
744 * http://www.jedec.org/standards-documents/results/jesd220
745 */
746 static const unsigned int controlPage[3];
747 static const unsigned int recoveryPage[3];
748 static const unsigned int cachingPage[5];
749
750 /*
751 * SCSI command set; defined in
752 * http://www.jedec.org/standards-documents/results/jesd220
753 */
754 enum SCSICommandSet {
755 SCSIInquiry = 0x12,
756 SCSIRead6 = 0x08,
757 SCSIRead10 = 0x28,
758 SCSIRead16 = 0x88,
759 SCSIReadCapacity10 = 0x25,
760 SCSIReadCapacity16 = 0x9E,
761 SCSIReportLUNs = 0xA0,
762 SCSIStartStop = 0x1B,
763 SCSITestUnitReady = 0x00,
764 SCSIVerify10 = 0x2F,
765 SCSIWrite6 = 0x0A,
766 SCSIWrite10 = 0x2A,
767 SCSIWrite16 = 0x8A,
768 SCSIFormatUnit = 0x04,
769 SCSISendDiagnostic = 0x1D,
770 SCSISynchronizeCache = 0x35,
771 //UFS SCSI additional command set for full functionality
772 SCSIModeSelect10 = 0x55,
773 SCSIModeSense6 = 0x1A,
774 SCSIModeSense10 = 0x5A,
775 SCSIRequestSense = 0x03,
776 SCSIUnmap = 0x42,
777 SCSIWriteBuffer = 0x3B,
778 SCSIReadBuffer = 0x3C,
779 //SCSI commands not supported by UFS; but Linux send them anyway
780 SCSIMaintenanceIn = 0xA3
781 };
782
783 /*
784 * SCSI status codes; defined in
785 * http://www.jedec.org/standards-documents/results/jesd220
786 */
787 enum SCSIStatusCodes {
788 SCSIGood = 0x00,
789 SCSICheckCondition = 0x02,
790 SCSIConditionGood = 0x04,
791 SCSIBusy = 0x08,
792 SCSIIntermediateGood = 0x10,
793 SCSIIntermediatCGood = 0x14,
794 SCSIReservationConflict = 0x18,
795 SCSICommandTerminated = 0x22,
796 SCSITaskSetFull = 0x28,
797 SCSIACAActive = 0x30,
798 SCSITaskAborted = 0x40
799 };
800
801 /*
802 * SCSI sense codes; defined in
803 * http://www.jedec.org/standards-documents/results/jesd220
804 */
805 enum SCSISenseCodes {
806 SCSINoSense = 0x00,
807 SCSIRecoverdError = 0x01,
808 SCSINotReady = 0x02,
809 SCSIMediumError = 0x03,
810 SCSIHardwareError = 0x04,
811 SCSIIllegalRequest = 0x05,
812 SCSIUnitAttention = 0x06,
813 SCSIDataProtect = 0x07,
814 SCSIBlankCheck = 0x08,
815 SCSIAbortedCommand = 0x0B,
816 SCSIVolumeOverflow = 0x0D,
817 SCSIMisCompare = 0x0E
818 };
819
820 };
821
822 //All access functions are inherrited; no need to make them public
823 /**
824 * Address range functions
825 */
826 AddrRangeList getAddrRanges() const;
827
828 /**
829 * register access functions
830 */
831 Tick read(PacketPtr pkt);
832 Tick write(PacketPtr pkt);
833 // end of access functions
834
835 /**
836 * Initialization function. Sets the sefault HCI register values
837 */
838 void setValues();
839
840 /**
841 * Handler functions. Each function handles a different stage of the
842 * transfer. Note that the UFS protocol specifies three types of messages
843 * to the host (and devices):
844 * 1: Command (to Host specifically)
845 * 2: Task (to device; to control flow, not for data)
846 * 3: Transfer (to device; to transfer data)
847 */
848 /**
849 * request handler. This function finds the cause of the request and
850 * triggers the right follow-up action (command handler, task handler,
851 * or transferhandler)
852 */
853 void requestHandler();
854
855 /**
856 * Command handler function. Handles the command send to the Host
857 * controller
858 */
859 void commandHandler();
860
861 /**
862 * Task Start function. Starts the task handler once the task data
863 * structure has arrived
864 */
865 void taskStart();
866
867 /**
868 * Task handler function. Handles the tasks send to the devices
869 * because there are not many tasks implemented yet this is kept in the
870 * Host controller layer
871 */
872 void taskHandler(struct UTPUPIUTaskReq* request_in,
873 uint32_t req_pos, Addr finaladdress, uint32_t finalsize);
874
875 /**
876 * Transfer Start function. Starts the transfer handler once the transfer
877 * data structure has arrived
878 */
879 void transferStart();
880
881 /**
882 * Transfer handler function. Handles the transfers send to the devices
883 * Important to understand here is that a Logic unit is not a device (a
884 * device can contain multiple logic units). This function analyses the
885 * first data structure that has been transfered. Which will tell the
886 * host to expect SCSI frames for the rest of the transaction. Note that
887 * the host has no indication whatsoever which LU to address. That will
888 * follow in the next transaction.
889 */
890 void transferHandler(struct UTPTransferReqDesc*
891 request_in, int req_pos, Addr finaladdress,
892 uint32_t finalsize, uint32_t done);
893
894 /**
895 * Transfer SCSI function. Determines which Logic unit to address and
896 * starts the SCSI resume function
897 */
898 void SCSIStart();
899
900 /**
901 * Starts the scsi handling function in the apropriate Logic unit,
902 * prepares the right data transfer scheme and kicks it off.
903 */
904 void SCSIResume(uint32_t lun_id);
905
906 /**
907 * LU callback function to indicate that the action has completed.
908 */
909 void LUNSignal();
910
911 /**
912 * transfer done, the beginning of the final stage of the transfer.
913 * Acknowledges UPIU frame and prepares the UTP response frame
914 */
915 void transferDone(Addr responseStartAddr, uint32_t req_pos,
916 struct UTPUPIURSP request_out, uint32_t size,
917 Addr address, uint8_t* destination, bool finished,
918 uint32_t lun_id);
919 /**
920 * final UTP, sends the last acknowledge data structure to the system;
921 * prepares the clean up functions.
922 */
923 void finalUTP();
924
925 /**
926 * Interrupt control functions
927 */
928 void clearInterrupt();
929 void generateInterrupt();
930
931 /**
932 * DMA transfer functions
933 * These allow the host to push/pull the data to the memory
934 * The provided event indicates what the next phase it that will handle
935 * the obtained data, or what the follow up action is once the data has
936 * been pushed to the memory
937 */
938 void writeDevice(Event* additional_action, bool toDisk, Addr start,
939 int size, uint8_t* destination, uint64_t SCSIDiskOffset,
940 uint32_t lun_id);
941 void readDevice(bool lastTransfer, Addr SCSIStart, uint32_t SCSISize,
942 uint8_t* SCSIDestination, bool no_cache,
943 Event* additional_action);
944
945 /**
946 * Disk transfer management functions
947 * these set up the queues, and initiated them, leading to the data
948 * transaction timing model based on the scatter gather list constructed
949 * in SCSIresume.
950 */
951 void manageWriteTransfer(uint8_t LUN, uint64_t offset, uint32_t
952 sg_table_length, struct UFSHCDSGEntry* sglist);
953 void manageReadTransfer(uint32_t size, uint32_t LUN, uint64_t offset,
954 uint32_t sg_table_length,
955 struct UFSHCDSGEntry* sglist);
956
957 /**
958 * Read done
959 * Started at the end of a transaction after the last read action. Cleans
960 * up UTP descriptor and other remaining data structures. It also raises
961 * the interrupt.
962 */
963 void readDone();
964
965 /**
966 * Write done
967 * After a DMA write with data intended for the disk, this function is
968 * called. It ensures that the disk image is modified, and that the
969 * correct timing function is triggered.
970 */
971 void writeDone();
972
973 /**
974 * Read callback
975 * Call back function for the logic units to indicate the completion of
976 * a read action. Note that this is needed because the read functionality
977 * needs to push data structures back to the memory.
978 */
979 void readCallback();
980
981 /**
982 * Read garbage
983 * A read from disk data structure can vary in size and is therefor
984 * allocated on creation. It can only be destroyed once that particular
985 * read action has completed. This function is called on completion of a
986 * read from disk action to handle this.
987 */
988 void readGarbage();
989
990 /**register statistics*/
991 void regStats();
992
993 /**
994 * Host controller information
995 */
996 const Addr pioAddr;
997 const Addr pioSize;
998 const Tick pioDelay;
999 const int intNum;
1000 BaseGic* gic;
1001 const uint32_t lunAvail;
1002 const uint8_t UFSSlots;
1003
1004 /**
1005 * Host controller memory
1006 */
1007 HCIMem UFSHCIMem;
1008
1009 /**
1010 * Track number of DMA transactions in progress
1011 */
1012 int readPendingNum;
1013 int writePendingNum;
1014
1015 /**
1016 * Statistics helper variables
1017 * Active doorbells indicates how many doorbells are in teh process of
1018 * being handled.
1019 * Pending doorbells have been handled and are waiting to be acknowledged
1020 * by the host system.
1021 * The doorbell register is 32 bits wide, so one byte is enough to keep
1022 * track of the numbers
1023 */
1024 uint8_t activeDoorbells;
1025 uint8_t pendingDoorbells;
1026
1027 /**
1028 * interrupt verification
1029 * This keeps track of the number of interrupts generated. It is usefull
1030 * for debug purposes. Make sure that the implemented driver prints the
1031 * number of interrupts it has handled so far to fully benefit from this
1032 * feature.
1033 */
1034 uint32_t countInt;
1035
1036 /**
1037 * Track the transfer
1038 * This is allows the driver to "group" certain transfers together by
1039 * using a tag in the UPIU. The messages with the same tag should be
1040 * handled together, i.e. their doorbells should be cleared when they are
1041 * all done. but we need to keep track of the ones we already handled,
1042 * this integer shadows the doorbells to allow this behaviour.
1043 */
1044 uint32_t transferTrack;
1045 uint32_t taskCommandTrack;
1046
1047 /**
1048 * Helper for latency stats
1049 * These variables keep track of the latency for every doorbell.
1050 * Eventually the latenmcies will be put in a histogram.
1051 */
1052 Tick transactionStart[32];
1053 Tick idlePhaseStart;
1054
1055 /**
1056 * drain manager
1057 * Needed to be able to implement checkpoint functionality
1058 */
1059
1060 DrainManager *drainManager;
1061
1062 /**
1063 * logic units connected to the UFS Host device
1064 * Note again that the "device" as such is represented by one or multiple
1065 * logic units.
1066 */
1067 std::vector<UFSSCSIDevice*> UFSDevice;
1068
1069 /**
1070 * SCSI reply structure, used for direct answering. Might be refered to
1071 * during the assembly of the reply (data, and response; e.g. if
1072 * something goes wrong along the way, the reply will be different)
1073 */
1074 struct SCSIReply request_out_datain;
1075
1076 /**
1077 * SCSI resume info
1078 * information structure for SCSI resume. it keeps track of all the
1079 * information that is needed to successfully complete the transaction
1080 * (response addresses, communicated information so far, etc.).
1081 */
1082 struct SCSIResumeInfo SCSIInfo;
1083
1084 /**
1085 * To finish the transaction one needs information about the original
1086 * message. This is stored in this queue
1087 * transferEnd uses the same structure as transferStartInfo, because all
1088 * the information it needs is in there. It improves readability in the
1089 * cc file.
1090 */
1091 std::deque<struct transferStart> transferEnd;
1092
1093 /**
1094 * When a task/transfer is started it needs information about the
1095 * task/transfer it is about to perform. This is defined in these
1096 * structures. If multiple tasks/transfers are issued at the same time,
1097 * they still need to be fetched one by one. They then need to be
1098 * executed in the order specified by the UFS standard (least significant
1099 * doorbell first). The tasks/transfers are placed in the queue in that
1100 * specific order.
1101 */
1102 std::deque<struct taskStart> taskInfo;
1103 std::deque<struct transferStart> transferStartInfo;
1104
1105 /**
1106 * Information to get a DMA transaction
1107 */
1108 std::deque<struct writeToDiskBurst> dmaWriteInfo;
1109
1110 /**
1111 * Information from DMA transaction to disk
1112 */
1113 std::deque<struct transferInfo> SSDWriteinfo;
1114
1115 /**
1116 * Information from the Disk, waiting to be pushed to the DMA
1117 */
1118 std::deque<struct transferInfo> SSDReadPending;
1119
1120 /**
1121 * garbage queue, ensure clearing of the allocated memory
1122 */
1123 std::deque<struct UTPTransferReqDesc*> garbage;
1124
1125 /**
1126 * RequestHandler stats
1127 */
1128 struct UFSHostDeviceStats stats;
1129
1130 /**
1131 * Transfer flow events
1132 * Basically these events form two queues, one from memory to UFS device
1133 * (DMA) and one from device to flash (SSD). The SSD "queue" is
1134 * maintained by the flash and the lun classes and does not form a queue
1135 * of events as such, but rather a queue of information. This can be done
1136 * because the flow of the events is completely in the control of these
1137 * classes. (Whereas in the DMA case we rely on an external class)
1138 */
1139 std::deque<EventWrapper<UFSHostDevice, &UFSHostDevice::readDone> >
1140 readDoneEvent;
1141 std::deque<EventWrapper<UFSHostDevice, &UFSHostDevice::writeDone> >
1142 writeDoneEvent;
1143
1144 /**
1145 * Callbacks for the logic units. One to indicate the completion of a
1146 * transaction, the other one to indicate the completion of a read
1147 * action.
1148 */
1149 Callback* transferDoneCallback;
1150 Callback* memReadCallback;
1151
1152 /**
1153 * The events that control the functionality.
1154 * After a doorbell has been set, either a taskevent or a transfer event
1155 * is scheduled. A transfer event might schedule a SCSI event, all events
1156 * sequences end with an UTP event, which can be considered as the event
1157 * which answers the doorbell.
1158 */
1159 /**
1160 * Wait for the SCSI specific data to arive
1161 */
1162 EventWrapper<UFSHostDevice, &UFSHostDevice::SCSIStart> SCSIResumeEvent;
1163
1164 /**
1165 * Wait for the moment where we can send the last frame
1166 */
1167 EventWrapper<UFSHostDevice, &UFSHostDevice::finalUTP> UTPEvent;
1168
1169 /**
1170 * Event after a read to clean up the UTP data structures
1171 */
1172 std::deque<EventWrapper<UFSHostDevice, &UFSHostDevice::readGarbage> >
1173 readGarbageEventQueue;
1174
1175 /**
1176 * Multiple tasks transfers can be scheduled at once for the device, the
1177 * only thing we know for sure about them is that they will happen in a
1178 * first come first serve order; hence we need to queue.
1179 */
1180 std::deque<EventWrapper<UFSHostDevice, &UFSHostDevice::taskStart> >
1181 taskEventQueue;
1182 std::deque<EventWrapper<UFSHostDevice, &UFSHostDevice::transferStart> >
1183 transferEventQueue;
1184
1185 /**
1186 * Bits of interest within UFS data packages
1187 */
1188 static const unsigned int UTPTransferREQCOMPL = 0x01;//UFS_BIT(0)
1189 static const unsigned int UTPTaskREQCOMPL = 0x200;//UFS_BIT(9)
1190 static const unsigned int UICCommandCOMPL = 0x400;//UFS_BIT(10)
1191 static const unsigned int UICCommandReady = 0x08;//UFS_BIT(3)
1192
1193 /*
1194 * UFSHCI Registers; please refer to
1195 * http://www.jedec.org/standards-documents/results/jesd223
1196 * for their definition.
1197 */
1198 enum UFSHCIRegisters {
1199 regControllerCapabilities = 0x00,
1200 regUFSVersion = 0x08,
1201 regControllerDEVID = 0x10,
1202 regControllerPRODID = 0x14,
1203 regInterruptStatus = 0x20,
1204 regInterruptEnable = 0x24,
1205 regControllerStatus = 0x30,
1206 regControllerEnable = 0x34,
1207 regUICErrorCodePHYAdapterLayer = 0x38,
1208 regUICErrorCodeDataLinkLayer = 0x3C,
1209 regUICErrorCodeNetworkLayer = 0x40,
1210 regUICErrorCodeTransportLayer = 0x44,
1211 regUICErrorCodeDME = 0x48,
1212 regUTPTransferREQINTAGGControl = 0x4C,
1213 regUTPTransferREQListBaseL = 0x50,
1214 regUTPTransferREQListBaseH = 0x54,
1215 regUTPTransferREQDoorbell = 0x58,
1216 regUTPTransferREQListClear = 0x5C,
1217 regUTPTransferREQListRunStop = 0x60,
1218 regUTPTaskREQListBaseL = 0x70,
1219 regUTPTaskREQListBaseH = 0x74,
1220 regUTPTaskREQDoorbell = 0x78,
1221 regUTPTaskREQListClear = 0x7C,
1222 regUTPTaskREQListRunStop = 0x80,
1223 regUICCommand = 0x90,
1224 regUICCommandArg1 = 0x94,
1225 regUICCommandArg2 = 0x98,
1226 regUICCommandArg3 = 0x9C
1227 };
1228};
1229
1230#endif //__DEV_ARM_UFS_DEVICE_HH__
| 180
181 private:
182 /**
183 * Host Controller Interface
184 * This is a set of registers that allow the driver to control the
185 * transactions to the flash devices.
186 * As defined in:
187 * http://www.jedec.org/standards-documents/results/jesd223
188 */
189 struct HCIMem {
190 /**
191 * Specify the host capabilities
192 */
193 uint32_t HCCAP;
194 uint32_t HCversion;
195 uint32_t HCHCDDID;
196 uint32_t HCHCPMID;
197
198 /**
199 * Operation and runtime registers
200 */
201 uint32_t ORInterruptStatus;
202 uint32_t ORInterruptEnable;
203 uint32_t ORHostControllerStatus;
204 uint32_t ORHostControllerEnable;
205 uint32_t ORUECPA;
206 uint32_t ORUECDL;
207 uint32_t ORUECN;
208 uint32_t ORUECT;
209 uint32_t ORUECDME;
210 uint32_t ORUTRIACR;
211
212 /**
213 * vendor specific register
214 */
215 uint32_t vendorSpecific;
216
217 /**
218 * Transfer control registers
219 */
220 uint32_t TRUTRLBA;
221 uint32_t TRUTRLBAU;
222 uint32_t TRUTRLDBR;
223 uint32_t TRUTRLCLR;
224 uint32_t TRUTRLRSR;
225
226 /**
227 * Task control registers
228 */
229 uint32_t TMUTMRLBA;
230 uint32_t TMUTMRLBAU;
231 uint32_t TMUTMRLDBR;
232 uint32_t TMUTMRLCLR;
233 uint32_t TMUTMRLRSR;
234
235 /**
236 * Command registers
237 */
238 uint32_t CMDUICCMDR;
239 uint32_t CMDUCMDARG1;
240 uint32_t CMDUCMDARG2;
241 uint32_t CMDUCMDARG3;
242 };
243
244 /**
245 * All the data structures are defined in the UFS standard
246 * This standard be found at the JEDEC website free of charge
247 * (login required):
248 * http://www.jedec.org/standards-documents/results/jesd220
249 */
250
251 /**
252 * struct UTPUPIUHeader - UPIU header structure
253 * dWord0: UPIU header DW-0
254 * dWord1: UPIU header DW-1
255 * dWord2: UPIU header DW-2
256 */
257 struct UTPUPIUHeader {
258 uint32_t dWord0;
259 uint32_t dWord1;
260 uint32_t dWord2;
261 };
262
263 /**
264 * struct UTPUPIURSP - Response UPIU structure
265 * header: UPIU header DW-0 to DW-2
266 * residualTransferCount: Residual transfer count DW-3
267 * reserved: Reserved DW-4 to DW-7
268 * senseDataLen: Sense data length DW-8 U16
269 * senseData: Sense data field DW-8 to DW-12
270 */
271 struct UTPUPIURSP {
272 struct UTPUPIUHeader header;
273 uint32_t residualTransferCount;
274 uint32_t reserved[4];
275 uint16_t senseDataLen;
276 uint8_t senseData[18];
277 };
278
279 /**
280 * struct UTPUPIUTaskReq - Task request UPIU structure
281 * header - UPIU header structure DW0 to DW-2
282 * inputParam1: Input param 1 DW-3
283 * inputParam2: Input param 2 DW-4
284 * inputParam3: Input param 3 DW-5
285 * reserved: Reserver DW-6 to DW-7
286 */
287 struct UTPUPIUTaskReq {
288 struct UTPUPIUHeader header;
289 uint32_t inputParam1;
290 uint32_t inputParam2;
291 uint32_t inputParam3;
292 uint32_t reserved[2];
293 };
294
295 /**
296 * struct UFSHCDSGEntry - UFSHCI PRD Entry
297 * baseAddr: Lower 32bit physical address DW-0
298 * upperAddr: Upper 32bit physical address DW-1
299 * reserved: Reserved for future use DW-2
300 * size: size of physical segment DW-3
301 */
302 struct UFSHCDSGEntry {
303 uint32_t baseAddr;
304 uint32_t upperAddr;
305 uint32_t reserved;
306 uint32_t size;
307 };
308
309 /**
310 * struct UTPTransferCMDDesc - UFS Commad Descriptor structure
311 * commandUPIU: Command UPIU Frame address
312 * responseUPIU: Response UPIU Frame address
313 * PRDTable: Physcial Region Descriptor
314 * All lengths as defined by JEDEC220
315 */
316 struct UTPTransferCMDDesc {
317 uint8_t commandUPIU[128];
318 uint8_t responseUPIU[128];
319 struct UFSHCDSGEntry PRDTable[128];
320 };
321
322 /**
323 * UPIU tranfer message.
324 */
325 struct UPIUMessage {
326 struct UTPUPIUHeader header;
327 uint32_t dataOffset;
328 uint32_t dataCount;
329 std::vector<uint32_t> dataMsg;
330 };
331
332 /**
333 * struct UTPTransferReqDesc - UTRD structure
334 * header: UTRD header DW-0 to DW-3
335 * commandDescBaseAddrLo: UCD base address low DW-4
336 * commandDescBaseAddrHi: UCD base address high DW-5
337 * responseUPIULength: response UPIU length DW-6
338 * responseUPIUOffset: response UPIU offset DW-6
339 * PRDTableLength: Physical region descriptor length DW-7
340 * PRDTableOffset: Physical region descriptor offset DW-7
341 */
342 struct UTPTransferReqDesc {
343
344 /**
345 * struct RequestDescHeader
346 * dword0: Descriptor Header DW0
347 * dword1: Descriptor Header DW1
348 * dword2: Descriptor Header DW2
349 * dword3: Descriptor Header DW3
350 */
351 struct RequestDescHeader {
352 uint32_t dWord0;
353 uint32_t dWord1;
354 uint32_t dWord2;
355 uint32_t dWord3;
356 } header;
357
358 /* DW 4-5*/
359 uint32_t commandDescBaseAddrLo;
360 uint32_t commandDescBaseAddrHi;
361
362 /* DW 6 */
363 uint16_t responseUPIULength;
364 uint16_t responseUPIUOffset;
365
366 /* DW 7 */
367 uint16_t PRDTableLength;
368 uint16_t PRDTableOffset;
369 };
370
371 /**
372 * SCSI reply structure. In here is all the information that is needed to
373 * build a SCSI reply.
374 */
375 struct SCSIReply {
376 uint8_t status;
377 uint32_t msgSize;
378 uint8_t LUN;
379 struct UPIUMessage message;
380 uint8_t senseSize;
381 uint8_t expectMore;//0x01 is for writes, 0x02 is for reads
382 uint64_t offset;
383 uint8_t senseCode[19];
384 };
385
386 /**
387 * Logic unit information structure. SCSI requires information of each LUN.
388 * This structure is defined in the SCSI standard, and can also be found in
389 * the UFS standard. http://www.jedec.org/standards-documents/results/jesd220
390 */
391 struct LUNInfo {
392 uint32_t dWord0;
393 uint32_t dWord1;
394 uint32_t vendor0;
395 uint32_t vendor1;
396 uint32_t product0;
397 uint32_t product1;
398 uint32_t product2;
399 uint32_t product3;
400 uint32_t productRevision;
401 };
402
403 /**
404 * Different events, and scenarios require different types of information.
405 * Keep in mind that for a read-from-disk transaction the host at first a
406 * datastructure fetches to determine where and what the command is, then the
407 * command fetches and the structure fetches to determine where the
408 * different read transactions should be placed and then transfers all the
409 * read fragments. It then answers to the original caller with two replies,
410 * one for the command, and one for UFS. Each of these stages trigger a
411 * different event, and each event needs to know what happened in the
412 * previous stage and what is going to happen in the current one. This
413 * happens also for writes, SCSI maintanance, UFS maintanance, command
414 * management and task management.
415 */
416
417 /**
418 * Transfer information.
419 * @filePointer this does not point to a file, but to a position on the disk
420 * image (which is from the software systems perspective a position in a file)
421 */
422 struct transferInfo {
423 std::vector <uint8_t> buffer;
424 uint32_t size;
425 uint64_t offset;
426 uint32_t filePointer;
427 uint32_t lunID;
428 };
429
430 /**
431 * transfer completion info.
432 * This information is needed by transferDone to finish the transfer.
433 */
434 struct transferDoneInfo {
435 Addr responseStartAddr;
436 uint32_t reqPos;
437 struct UTPUPIURSP requestOut;
438 uint32_t size;
439 Addr address;
440 uint8_t *destination;
441 bool finished;
442 uint32_t lunID;
443 };
444
445 /**
446 * Transfer start information.
447 */
448 struct transferStart {
449 struct UTPTransferReqDesc* destination;
450 uint32_t mask;
451 Addr address;
452 uint32_t size;
453 uint32_t done;
454 uint32_t lun_id;
455 };
456
457 /**
458 * Task start information. This is for the device, so no lun id needed.
459 */
460 struct taskStart {
461 struct UTPUPIUTaskReq destination;
462 uint32_t mask;
463 Addr address;
464 uint32_t size;
465 bool done;
466 };
467
468 /**
469 * After a SCSI command has been identified, the SCSI resume function will
470 * handle it. This information will provide context information.
471 */
472 struct SCSIResumeInfo {
473 struct UTPTransferReqDesc* RequestIn;
474 int reqPos;
475 Addr finalAddress;
476 uint32_t finalSize;
477 std::vector <uint8_t> destination;
478 uint32_t done;
479 };
480
481 /**
482 * Disk transfer burst information. Needed to allow communication between the
483 * disk transactions and dma transactions.
484 */
485 struct writeToDiskBurst {
486 Addr start;
487 uint64_t SCSIDiskOffset;
488 uint32_t size;
489 uint32_t LUN;
490 };
491
492 /**
493 * Statistics
494 */
495 struct UFSHostDeviceStats {
496 /** Queue lengths */
497 Stats::Scalar currentSCSIQueue;
498 Stats::Scalar currentReadSSDQueue;
499 Stats::Scalar currentWriteSSDQueue;
500
501 /** Amount of data read/written */
502 Stats::Scalar totalReadSSD;
503 Stats::Scalar totalWrittenSSD;
504 Stats::Scalar totalReadDiskTransactions;
505 Stats::Scalar totalWriteDiskTransactions;
506 Stats::Scalar totalReadUFSTransactions;
507 Stats::Scalar totalWriteUFSTransactions;
508
509 /** Average bandwidth for reads and writes */
510 Stats::Formula averageReadSSDBW;
511 Stats::Formula averageWriteSSDBW;
512
513 /** Average Queue lengths*/
514 Stats::Average averageSCSIQueue;
515 Stats::Average averageReadSSDQueue;
516 Stats::Average averageWriteSSDQueue;
517
518 /** Number of doorbells rung*/
519 Stats::Formula curDoorbell;
520 Stats::Scalar maxDoorbell;
521 Stats::Average averageDoorbell;
522
523 /** Histogram of latencies*/
524 Stats::Histogram transactionLatency;
525 Stats::Histogram idleTimes;
526 };
527
528 /**
529 * device layer: This is your Logic unit
530 * This layer implements the SCSI functionality of the UFS Device
531 * One logic unit controls one or more disk partitions
532 */
533 class UFSSCSIDevice: SimObject
534 {
535 public:
536 /**
537 * Constructor and destructor
538 */
539 UFSSCSIDevice(const UFSHostDeviceParams* p, uint32_t lun_id, Callback*
540 transfer_cb, Callback *read_cb);
541 ~UFSSCSIDevice();
542
543 /**
544 * SCSI command handle function; determines what the command is and
545 * returns a reply structure that allows the host device to continue
546 * with the transfer.
547 */
548 struct SCSIReply SCSICMDHandle(uint32_t* SCSI_msg);
549
550 /**
551 * Disk access functions. These will transfer the data from/to the disk
552 */
553
554 /**
555 * Read flash. read the data from the disk image. This function
556 * doesn't model timing behaviour
557 */
558 void readFlash(uint8_t* readaddr, uint64_t offset, uint32_t size);
559
560 /**
561 * Write flash. write the data to the disk image. This function
562 * doesn't model timing behaviour
563 */
564 void writeFlash(uint8_t* writeaddr, uint64_t offset, uint32_t size);
565
566 /**
567 * finished command. Probe to find out wether this logic unit
568 * finished its transfer and triggered the callback; The host needs
569 * this to handle the final part of the transaction.
570 */
571 bool finishedCommand() const {return transferCompleted;};
572
573 /**
574 * Clear signal. Handle for the host to clear the transfer complete
575 * signal.
576 */
577 void clearSignal() {transferCompleted = false;};
578
579 /**
580 * Finished read. Probe to find out which logic unit finished its
581 * read. This is needed, because multiple units can do transactions
582 * at the same time, and need to push back data at the right time in
583 * the right order. (because writes work the other way round, they do
584 * not need this mechanism)
585 */
586 bool finishedRead() const {return readCompleted;};
587
588 /**
589 * Clear signal. Handle for the host to clear the read complete
590 * signal.
591 */
592 void clearReadSignal() {readCompleted = false;};
593
594 /**
595 * Start the transactions to (and from) the disk
596 * The host will queue all the transactions. Once the next phase
597 * commences, this function should be started.
598 */
599 void SSDReadStart(uint32_t total_read);
600 void SSDWriteStart();
601
602 /**
603 * Sets total amount of write transactions that needs to be made.
604 * First they need to be fetched via DMA, so this value is needed in
605 * a later stage.
606 */
607 void setTotalWrite(uint32_t total_write) {totalWrite = total_write;};
608
609 /**
610 * End of transfer information
611 */
612 transferDoneInfo transferInfo;
613
614 /**
615 * Information message queues, as there can be multiple messages
616 * queued for handling in this system. These are the main
617 * communication interfaces between the Host and the device layers
618 */
619
620 /**
621 * SCSIInfoQueue: each LU handles its own SCSI commands.
622 */
623 std::deque<struct SCSIResumeInfo> SCSIInfoQueue;
624
625 /**
626 * SSDReadInfo: Structure from disk to dma, that contains data, and
627 * helper info to get it to the right place in the memory.
628 */
629 std::deque<struct transferInfo> SSDReadInfo;
630
631 /**
632 * SSDWriteDoneInfo: Structure from dma to disk, that contains data,
633 * and helper info to get it to the right place in the memory.
634 * The done is added because it is going to the last phase of the
635 * write transfer.
636 */
637 std::deque<struct transferInfo> SSDWriteDoneInfo;
638
639 private:
640 /**
641 * Functions to indicate that the action to the SSD has completed.
642 */
643 /**
644 * Read Call back; This is the callback function for the memory model
645 */
646 void readCallback();
647
648 /**
649 * SSD Read done; Determines if the final callback of the transaction
650 * should be made at the end of a read transfer.
651 */
652 void SSDReadDone();
653
654 /**
655 * SSD Write Done; This is the callback function for the memory model.
656 */
657 void SSDWriteDone();
658
659 /**
660 * Status of SCSI. This may be linked to a status check in the future.
661 * For now it (mainly) fills a data structure with sense information
662 * for a successfull transaction
663 */
664 void statusCheck(uint8_t status, uint8_t* sensecodelist);
665
666 /**
667 * set signal to indicate that the transaction has been completed.
668 */
669 void setSignal() {transferCompleted = true;};
670
671 /**
672 * set signal to indicate that the read action has been completed
673 */
674 void setReadSignal() {readCompleted = true;};
675
676 /**
677 * The objects this model links to.
678 * 1: the disk data model
679 * 2: the memory timing model
680 */
681 DiskImage* flashDisk;
682 AbstractNVM* flashDevice;
683
684 /**
685 * Logic unit dimensions
686 */
687 const uint32_t blkSize;
688 const uint32_t lunAvail;
689 const uint64_t diskSize;
690 const uint32_t capacityLower;
691 const uint32_t capacityUpper;
692
693 /**
694 * Logic unit info; needed for SCSI Info messages and LU
695 * identification
696 */
697 struct LUNInfo lunInfo;
698 const uint32_t lunID;
699
700 /**
701 * Signals to Host layer
702 * 1: signal for transaction completion
703 * 2: signal for read action completion
704 */
705 bool transferCompleted;
706 bool readCompleted;
707
708 /**
709 * Total amount transactions that need to be made
710 */
711 uint32_t totalRead;
712 uint32_t totalWrite;
713
714 /**
715 * transaction progress tracking
716 */
717 uint32_t amountOfWriteTransfers;
718 uint32_t amountOfReadTransfers;
719
720 /**
721 * Callbacks between Host and Device
722 */
723 Callback* signalDone;
724 Callback* deviceReadCallback;
725
726 /**
727 * Callbacks between Device and Memory
728 */
729 Callback* memReadCallback;
730 Callback* memWriteCallback;
731
732 /*
733 * Default response header layout. For more information refer to
734 * chapter 7 http://www.jedec.org/standards-documents/results/jesd220
735 */
736 static const unsigned int UPIUHeaderDataIndWord0 = 0x0000C022;
737 static const unsigned int UPIUHeaderDataIndWord1 = 0x00000000;
738 static const unsigned int UPIUHeaderDataIndWord2 = 0x40000000;
739
740 /*
741 * SCSI mode pages values assigned in ufs_device.cc
742 * The mode pages give device specific information via the SCSI
743 * protocol. They are defined in
744 * http://www.jedec.org/standards-documents/results/jesd220
745 */
746 static const unsigned int controlPage[3];
747 static const unsigned int recoveryPage[3];
748 static const unsigned int cachingPage[5];
749
750 /*
751 * SCSI command set; defined in
752 * http://www.jedec.org/standards-documents/results/jesd220
753 */
754 enum SCSICommandSet {
755 SCSIInquiry = 0x12,
756 SCSIRead6 = 0x08,
757 SCSIRead10 = 0x28,
758 SCSIRead16 = 0x88,
759 SCSIReadCapacity10 = 0x25,
760 SCSIReadCapacity16 = 0x9E,
761 SCSIReportLUNs = 0xA0,
762 SCSIStartStop = 0x1B,
763 SCSITestUnitReady = 0x00,
764 SCSIVerify10 = 0x2F,
765 SCSIWrite6 = 0x0A,
766 SCSIWrite10 = 0x2A,
767 SCSIWrite16 = 0x8A,
768 SCSIFormatUnit = 0x04,
769 SCSISendDiagnostic = 0x1D,
770 SCSISynchronizeCache = 0x35,
771 //UFS SCSI additional command set for full functionality
772 SCSIModeSelect10 = 0x55,
773 SCSIModeSense6 = 0x1A,
774 SCSIModeSense10 = 0x5A,
775 SCSIRequestSense = 0x03,
776 SCSIUnmap = 0x42,
777 SCSIWriteBuffer = 0x3B,
778 SCSIReadBuffer = 0x3C,
779 //SCSI commands not supported by UFS; but Linux send them anyway
780 SCSIMaintenanceIn = 0xA3
781 };
782
783 /*
784 * SCSI status codes; defined in
785 * http://www.jedec.org/standards-documents/results/jesd220
786 */
787 enum SCSIStatusCodes {
788 SCSIGood = 0x00,
789 SCSICheckCondition = 0x02,
790 SCSIConditionGood = 0x04,
791 SCSIBusy = 0x08,
792 SCSIIntermediateGood = 0x10,
793 SCSIIntermediatCGood = 0x14,
794 SCSIReservationConflict = 0x18,
795 SCSICommandTerminated = 0x22,
796 SCSITaskSetFull = 0x28,
797 SCSIACAActive = 0x30,
798 SCSITaskAborted = 0x40
799 };
800
801 /*
802 * SCSI sense codes; defined in
803 * http://www.jedec.org/standards-documents/results/jesd220
804 */
805 enum SCSISenseCodes {
806 SCSINoSense = 0x00,
807 SCSIRecoverdError = 0x01,
808 SCSINotReady = 0x02,
809 SCSIMediumError = 0x03,
810 SCSIHardwareError = 0x04,
811 SCSIIllegalRequest = 0x05,
812 SCSIUnitAttention = 0x06,
813 SCSIDataProtect = 0x07,
814 SCSIBlankCheck = 0x08,
815 SCSIAbortedCommand = 0x0B,
816 SCSIVolumeOverflow = 0x0D,
817 SCSIMisCompare = 0x0E
818 };
819
820 };
821
822 //All access functions are inherrited; no need to make them public
823 /**
824 * Address range functions
825 */
826 AddrRangeList getAddrRanges() const;
827
828 /**
829 * register access functions
830 */
831 Tick read(PacketPtr pkt);
832 Tick write(PacketPtr pkt);
833 // end of access functions
834
835 /**
836 * Initialization function. Sets the sefault HCI register values
837 */
838 void setValues();
839
840 /**
841 * Handler functions. Each function handles a different stage of the
842 * transfer. Note that the UFS protocol specifies three types of messages
843 * to the host (and devices):
844 * 1: Command (to Host specifically)
845 * 2: Task (to device; to control flow, not for data)
846 * 3: Transfer (to device; to transfer data)
847 */
848 /**
849 * request handler. This function finds the cause of the request and
850 * triggers the right follow-up action (command handler, task handler,
851 * or transferhandler)
852 */
853 void requestHandler();
854
855 /**
856 * Command handler function. Handles the command send to the Host
857 * controller
858 */
859 void commandHandler();
860
861 /**
862 * Task Start function. Starts the task handler once the task data
863 * structure has arrived
864 */
865 void taskStart();
866
867 /**
868 * Task handler function. Handles the tasks send to the devices
869 * because there are not many tasks implemented yet this is kept in the
870 * Host controller layer
871 */
872 void taskHandler(struct UTPUPIUTaskReq* request_in,
873 uint32_t req_pos, Addr finaladdress, uint32_t finalsize);
874
875 /**
876 * Transfer Start function. Starts the transfer handler once the transfer
877 * data structure has arrived
878 */
879 void transferStart();
880
881 /**
882 * Transfer handler function. Handles the transfers send to the devices
883 * Important to understand here is that a Logic unit is not a device (a
884 * device can contain multiple logic units). This function analyses the
885 * first data structure that has been transfered. Which will tell the
886 * host to expect SCSI frames for the rest of the transaction. Note that
887 * the host has no indication whatsoever which LU to address. That will
888 * follow in the next transaction.
889 */
890 void transferHandler(struct UTPTransferReqDesc*
891 request_in, int req_pos, Addr finaladdress,
892 uint32_t finalsize, uint32_t done);
893
894 /**
895 * Transfer SCSI function. Determines which Logic unit to address and
896 * starts the SCSI resume function
897 */
898 void SCSIStart();
899
900 /**
901 * Starts the scsi handling function in the apropriate Logic unit,
902 * prepares the right data transfer scheme and kicks it off.
903 */
904 void SCSIResume(uint32_t lun_id);
905
906 /**
907 * LU callback function to indicate that the action has completed.
908 */
909 void LUNSignal();
910
911 /**
912 * transfer done, the beginning of the final stage of the transfer.
913 * Acknowledges UPIU frame and prepares the UTP response frame
914 */
915 void transferDone(Addr responseStartAddr, uint32_t req_pos,
916 struct UTPUPIURSP request_out, uint32_t size,
917 Addr address, uint8_t* destination, bool finished,
918 uint32_t lun_id);
919 /**
920 * final UTP, sends the last acknowledge data structure to the system;
921 * prepares the clean up functions.
922 */
923 void finalUTP();
924
925 /**
926 * Interrupt control functions
927 */
928 void clearInterrupt();
929 void generateInterrupt();
930
931 /**
932 * DMA transfer functions
933 * These allow the host to push/pull the data to the memory
934 * The provided event indicates what the next phase it that will handle
935 * the obtained data, or what the follow up action is once the data has
936 * been pushed to the memory
937 */
938 void writeDevice(Event* additional_action, bool toDisk, Addr start,
939 int size, uint8_t* destination, uint64_t SCSIDiskOffset,
940 uint32_t lun_id);
941 void readDevice(bool lastTransfer, Addr SCSIStart, uint32_t SCSISize,
942 uint8_t* SCSIDestination, bool no_cache,
943 Event* additional_action);
944
945 /**
946 * Disk transfer management functions
947 * these set up the queues, and initiated them, leading to the data
948 * transaction timing model based on the scatter gather list constructed
949 * in SCSIresume.
950 */
951 void manageWriteTransfer(uint8_t LUN, uint64_t offset, uint32_t
952 sg_table_length, struct UFSHCDSGEntry* sglist);
953 void manageReadTransfer(uint32_t size, uint32_t LUN, uint64_t offset,
954 uint32_t sg_table_length,
955 struct UFSHCDSGEntry* sglist);
956
957 /**
958 * Read done
959 * Started at the end of a transaction after the last read action. Cleans
960 * up UTP descriptor and other remaining data structures. It also raises
961 * the interrupt.
962 */
963 void readDone();
964
965 /**
966 * Write done
967 * After a DMA write with data intended for the disk, this function is
968 * called. It ensures that the disk image is modified, and that the
969 * correct timing function is triggered.
970 */
971 void writeDone();
972
973 /**
974 * Read callback
975 * Call back function for the logic units to indicate the completion of
976 * a read action. Note that this is needed because the read functionality
977 * needs to push data structures back to the memory.
978 */
979 void readCallback();
980
981 /**
982 * Read garbage
983 * A read from disk data structure can vary in size and is therefor
984 * allocated on creation. It can only be destroyed once that particular
985 * read action has completed. This function is called on completion of a
986 * read from disk action to handle this.
987 */
988 void readGarbage();
989
990 /**register statistics*/
991 void regStats();
992
993 /**
994 * Host controller information
995 */
996 const Addr pioAddr;
997 const Addr pioSize;
998 const Tick pioDelay;
999 const int intNum;
1000 BaseGic* gic;
1001 const uint32_t lunAvail;
1002 const uint8_t UFSSlots;
1003
1004 /**
1005 * Host controller memory
1006 */
1007 HCIMem UFSHCIMem;
1008
1009 /**
1010 * Track number of DMA transactions in progress
1011 */
1012 int readPendingNum;
1013 int writePendingNum;
1014
1015 /**
1016 * Statistics helper variables
1017 * Active doorbells indicates how many doorbells are in teh process of
1018 * being handled.
1019 * Pending doorbells have been handled and are waiting to be acknowledged
1020 * by the host system.
1021 * The doorbell register is 32 bits wide, so one byte is enough to keep
1022 * track of the numbers
1023 */
1024 uint8_t activeDoorbells;
1025 uint8_t pendingDoorbells;
1026
1027 /**
1028 * interrupt verification
1029 * This keeps track of the number of interrupts generated. It is usefull
1030 * for debug purposes. Make sure that the implemented driver prints the
1031 * number of interrupts it has handled so far to fully benefit from this
1032 * feature.
1033 */
1034 uint32_t countInt;
1035
1036 /**
1037 * Track the transfer
1038 * This is allows the driver to "group" certain transfers together by
1039 * using a tag in the UPIU. The messages with the same tag should be
1040 * handled together, i.e. their doorbells should be cleared when they are
1041 * all done. but we need to keep track of the ones we already handled,
1042 * this integer shadows the doorbells to allow this behaviour.
1043 */
1044 uint32_t transferTrack;
1045 uint32_t taskCommandTrack;
1046
1047 /**
1048 * Helper for latency stats
1049 * These variables keep track of the latency for every doorbell.
1050 * Eventually the latenmcies will be put in a histogram.
1051 */
1052 Tick transactionStart[32];
1053 Tick idlePhaseStart;
1054
1055 /**
1056 * drain manager
1057 * Needed to be able to implement checkpoint functionality
1058 */
1059
1060 DrainManager *drainManager;
1061
1062 /**
1063 * logic units connected to the UFS Host device
1064 * Note again that the "device" as such is represented by one or multiple
1065 * logic units.
1066 */
1067 std::vector<UFSSCSIDevice*> UFSDevice;
1068
1069 /**
1070 * SCSI reply structure, used for direct answering. Might be refered to
1071 * during the assembly of the reply (data, and response; e.g. if
1072 * something goes wrong along the way, the reply will be different)
1073 */
1074 struct SCSIReply request_out_datain;
1075
1076 /**
1077 * SCSI resume info
1078 * information structure for SCSI resume. it keeps track of all the
1079 * information that is needed to successfully complete the transaction
1080 * (response addresses, communicated information so far, etc.).
1081 */
1082 struct SCSIResumeInfo SCSIInfo;
1083
1084 /**
1085 * To finish the transaction one needs information about the original
1086 * message. This is stored in this queue
1087 * transferEnd uses the same structure as transferStartInfo, because all
1088 * the information it needs is in there. It improves readability in the
1089 * cc file.
1090 */
1091 std::deque<struct transferStart> transferEnd;
1092
1093 /**
1094 * When a task/transfer is started it needs information about the
1095 * task/transfer it is about to perform. This is defined in these
1096 * structures. If multiple tasks/transfers are issued at the same time,
1097 * they still need to be fetched one by one. They then need to be
1098 * executed in the order specified by the UFS standard (least significant
1099 * doorbell first). The tasks/transfers are placed in the queue in that
1100 * specific order.
1101 */
1102 std::deque<struct taskStart> taskInfo;
1103 std::deque<struct transferStart> transferStartInfo;
1104
1105 /**
1106 * Information to get a DMA transaction
1107 */
1108 std::deque<struct writeToDiskBurst> dmaWriteInfo;
1109
1110 /**
1111 * Information from DMA transaction to disk
1112 */
1113 std::deque<struct transferInfo> SSDWriteinfo;
1114
1115 /**
1116 * Information from the Disk, waiting to be pushed to the DMA
1117 */
1118 std::deque<struct transferInfo> SSDReadPending;
1119
1120 /**
1121 * garbage queue, ensure clearing of the allocated memory
1122 */
1123 std::deque<struct UTPTransferReqDesc*> garbage;
1124
1125 /**
1126 * RequestHandler stats
1127 */
1128 struct UFSHostDeviceStats stats;
1129
1130 /**
1131 * Transfer flow events
1132 * Basically these events form two queues, one from memory to UFS device
1133 * (DMA) and one from device to flash (SSD). The SSD "queue" is
1134 * maintained by the flash and the lun classes and does not form a queue
1135 * of events as such, but rather a queue of information. This can be done
1136 * because the flow of the events is completely in the control of these
1137 * classes. (Whereas in the DMA case we rely on an external class)
1138 */
1139 std::deque<EventWrapper<UFSHostDevice, &UFSHostDevice::readDone> >
1140 readDoneEvent;
1141 std::deque<EventWrapper<UFSHostDevice, &UFSHostDevice::writeDone> >
1142 writeDoneEvent;
1143
1144 /**
1145 * Callbacks for the logic units. One to indicate the completion of a
1146 * transaction, the other one to indicate the completion of a read
1147 * action.
1148 */
1149 Callback* transferDoneCallback;
1150 Callback* memReadCallback;
1151
1152 /**
1153 * The events that control the functionality.
1154 * After a doorbell has been set, either a taskevent or a transfer event
1155 * is scheduled. A transfer event might schedule a SCSI event, all events
1156 * sequences end with an UTP event, which can be considered as the event
1157 * which answers the doorbell.
1158 */
1159 /**
1160 * Wait for the SCSI specific data to arive
1161 */
1162 EventWrapper<UFSHostDevice, &UFSHostDevice::SCSIStart> SCSIResumeEvent;
1163
1164 /**
1165 * Wait for the moment where we can send the last frame
1166 */
1167 EventWrapper<UFSHostDevice, &UFSHostDevice::finalUTP> UTPEvent;
1168
1169 /**
1170 * Event after a read to clean up the UTP data structures
1171 */
1172 std::deque<EventWrapper<UFSHostDevice, &UFSHostDevice::readGarbage> >
1173 readGarbageEventQueue;
1174
1175 /**
1176 * Multiple tasks transfers can be scheduled at once for the device, the
1177 * only thing we know for sure about them is that they will happen in a
1178 * first come first serve order; hence we need to queue.
1179 */
1180 std::deque<EventWrapper<UFSHostDevice, &UFSHostDevice::taskStart> >
1181 taskEventQueue;
1182 std::deque<EventWrapper<UFSHostDevice, &UFSHostDevice::transferStart> >
1183 transferEventQueue;
1184
1185 /**
1186 * Bits of interest within UFS data packages
1187 */
1188 static const unsigned int UTPTransferREQCOMPL = 0x01;//UFS_BIT(0)
1189 static const unsigned int UTPTaskREQCOMPL = 0x200;//UFS_BIT(9)
1190 static const unsigned int UICCommandCOMPL = 0x400;//UFS_BIT(10)
1191 static const unsigned int UICCommandReady = 0x08;//UFS_BIT(3)
1192
1193 /*
1194 * UFSHCI Registers; please refer to
1195 * http://www.jedec.org/standards-documents/results/jesd223
1196 * for their definition.
1197 */
1198 enum UFSHCIRegisters {
1199 regControllerCapabilities = 0x00,
1200 regUFSVersion = 0x08,
1201 regControllerDEVID = 0x10,
1202 regControllerPRODID = 0x14,
1203 regInterruptStatus = 0x20,
1204 regInterruptEnable = 0x24,
1205 regControllerStatus = 0x30,
1206 regControllerEnable = 0x34,
1207 regUICErrorCodePHYAdapterLayer = 0x38,
1208 regUICErrorCodeDataLinkLayer = 0x3C,
1209 regUICErrorCodeNetworkLayer = 0x40,
1210 regUICErrorCodeTransportLayer = 0x44,
1211 regUICErrorCodeDME = 0x48,
1212 regUTPTransferREQINTAGGControl = 0x4C,
1213 regUTPTransferREQListBaseL = 0x50,
1214 regUTPTransferREQListBaseH = 0x54,
1215 regUTPTransferREQDoorbell = 0x58,
1216 regUTPTransferREQListClear = 0x5C,
1217 regUTPTransferREQListRunStop = 0x60,
1218 regUTPTaskREQListBaseL = 0x70,
1219 regUTPTaskREQListBaseH = 0x74,
1220 regUTPTaskREQDoorbell = 0x78,
1221 regUTPTaskREQListClear = 0x7C,
1222 regUTPTaskREQListRunStop = 0x80,
1223 regUICCommand = 0x90,
1224 regUICCommandArg1 = 0x94,
1225 regUICCommandArg2 = 0x98,
1226 regUICCommandArg3 = 0x9C
1227 };
1228};
1229
1230#endif //__DEV_ARM_UFS_DEVICE_HH__
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