1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#ifndef __DEV_ARM_SP804_HH__
41#define __DEV_ARM_SP804_HH__
42
43#include "dev/arm/amba_device.hh"
44#include "params/Sp804.hh"
45
46/** @file
47 * This implements the dual Sp804 timer block
48 */
49
50class BaseGic;
51
52class Sp804 : public AmbaPioDevice
53{
54 protected:
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#ifndef __DEV_ARM_SP804_HH__
41#define __DEV_ARM_SP804_HH__
42
43#include "dev/arm/amba_device.hh"
44#include "params/Sp804.hh"
45
46/** @file
47 * This implements the dual Sp804 timer block
48 */
49
50class BaseGic;
51
52class Sp804 : public AmbaPioDevice
53{
54 protected:
|
55 class Timer
| 55 class Timer : public Serializable
|
56 {
57
58 public:
59 enum {
60 LoadReg = 0x00,
61 CurrentReg = 0x04,
62 ControlReg = 0x08,
63 IntClear = 0x0C,
64 RawISR = 0x10,
65 MaskedISR = 0x14,
66 BGLoad = 0x18,
67 Size = 0x20
68 };
69
70 BitUnion32(CTRL)
71 Bitfield<0> oneShot;
72 Bitfield<1> timerSize;
73 Bitfield<3,2> timerPrescale;
74 Bitfield<5> intEnable;
75 Bitfield<6> timerMode;
76 Bitfield<7> timerEnable;
77 EndBitUnion(CTRL)
78
79 protected:
80 std::string _name;
81
82 /** Pointer to parent class */
83 Sp804 *parent;
84
85 /** Number of interrupt to cause/clear */
86 const uint32_t intNum;
87
88 /** Number of ticks in a clock input */
89 const Tick clock;
90
91 /** Control register as specified above */
92 CTRL control;
93
94 /** If timer has caused an interrupt. This is irrespective of
95 * interrupt enable */
96 bool rawInt;
97
98 /** If an interrupt is currently pending. Logical and of CTRL.intEnable
99 * and rawInt */
100 bool pendingInt;
101
102 /** Value to load into counter when periodic mode reaches 0 */
103 uint32_t loadValue;
104
105 /** Called when the counter reaches 0 */
106 void counterAtZero();
107 EventWrapper<Timer, &Timer::counterAtZero> zeroEvent;
108
109 public:
110 /** Restart the counter ticking at val
111 * @param val the value to start at (pre-16 bit masking if en) */
112 void restartCounter(uint32_t val);
113
114 Timer(std::string __name, Sp804 *parent, int int_num, Tick clock);
115
116 std::string name() const { return _name; }
117
118 /** Handle read for a single timer */
119 void read(PacketPtr pkt, Addr daddr);
120
121 /** Handle write for a single timer */
122 void write(PacketPtr pkt, Addr daddr);
123
| 56 {
57
58 public:
59 enum {
60 LoadReg = 0x00,
61 CurrentReg = 0x04,
62 ControlReg = 0x08,
63 IntClear = 0x0C,
64 RawISR = 0x10,
65 MaskedISR = 0x14,
66 BGLoad = 0x18,
67 Size = 0x20
68 };
69
70 BitUnion32(CTRL)
71 Bitfield<0> oneShot;
72 Bitfield<1> timerSize;
73 Bitfield<3,2> timerPrescale;
74 Bitfield<5> intEnable;
75 Bitfield<6> timerMode;
76 Bitfield<7> timerEnable;
77 EndBitUnion(CTRL)
78
79 protected:
80 std::string _name;
81
82 /** Pointer to parent class */
83 Sp804 *parent;
84
85 /** Number of interrupt to cause/clear */
86 const uint32_t intNum;
87
88 /** Number of ticks in a clock input */
89 const Tick clock;
90
91 /** Control register as specified above */
92 CTRL control;
93
94 /** If timer has caused an interrupt. This is irrespective of
95 * interrupt enable */
96 bool rawInt;
97
98 /** If an interrupt is currently pending. Logical and of CTRL.intEnable
99 * and rawInt */
100 bool pendingInt;
101
102 /** Value to load into counter when periodic mode reaches 0 */
103 uint32_t loadValue;
104
105 /** Called when the counter reaches 0 */
106 void counterAtZero();
107 EventWrapper<Timer, &Timer::counterAtZero> zeroEvent;
108
109 public:
110 /** Restart the counter ticking at val
111 * @param val the value to start at (pre-16 bit masking if en) */
112 void restartCounter(uint32_t val);
113
114 Timer(std::string __name, Sp804 *parent, int int_num, Tick clock);
115
116 std::string name() const { return _name; }
117
118 /** Handle read for a single timer */
119 void read(PacketPtr pkt, Addr daddr);
120
121 /** Handle write for a single timer */
122 void write(PacketPtr pkt, Addr daddr);
123
|
124 void serialize(std::ostream &os);
125 void unserialize(Checkpoint *cp, const std::string §ion);
126
| 124 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
125 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
|
127 };
128
129 /** Pointer to the GIC for causing an interrupt */
130 BaseGic *gic;
131
132 /** Timers that do the actual work */
133 Timer timer0;
134 Timer timer1;
135
136 public:
137 typedef Sp804Params Params;
138 const Params *
139 params() const
140 {
141 return dynamic_cast<const Params *>(_params);
142 }
143 /**
144 * The constructor for RealView just registers itself with the MMU.
145 * @param p params structure
146 */
147 Sp804(Params *p);
148
149 /**
150 * Handle a read to the device
151 * @param pkt The memory request.
152 * @param data Where to put the data.
153 */
154 virtual Tick read(PacketPtr pkt);
155
156 /**
157 * All writes are simply ignored.
158 * @param pkt The memory request.
159 * @param data the data
160 */
161 virtual Tick write(PacketPtr pkt);
162
163
| 126 };
127
128 /** Pointer to the GIC for causing an interrupt */
129 BaseGic *gic;
130
131 /** Timers that do the actual work */
132 Timer timer0;
133 Timer timer1;
134
135 public:
136 typedef Sp804Params Params;
137 const Params *
138 params() const
139 {
140 return dynamic_cast<const Params *>(_params);
141 }
142 /**
143 * The constructor for RealView just registers itself with the MMU.
144 * @param p params structure
145 */
146 Sp804(Params *p);
147
148 /**
149 * Handle a read to the device
150 * @param pkt The memory request.
151 * @param data Where to put the data.
152 */
153 virtual Tick read(PacketPtr pkt);
154
155 /**
156 * All writes are simply ignored.
157 * @param pkt The memory request.
158 * @param data the data
159 */
160 virtual Tick write(PacketPtr pkt);
161
162
|
164 virtual void serialize(std::ostream &os);
165 virtual void unserialize(Checkpoint *cp, const std::string §ion);
| 163 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
164 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
|
166};
167
168
169#endif // __DEV_ARM_SP804_HH__
170
| 165};
166
167
168#endif // __DEV_ARM_SP804_HH__
169
|