1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#ifndef __DEV_ARM_SP804_HH__
41#define __DEV_ARM_SP804_HH__
42
43#include "base/range.hh"
44#include "dev/arm/amba_device.hh"
45#include "params/Sp804.hh"
46
47/** @file
48 * This implements the dual Sp804 timer block
49 */
50
51class Gic;
52
53class Sp804 : public AmbaDevice
54{
55 protected:
56 class Timer
57 {
58
59 public:
60 enum {
61 LoadReg = 0x00,
62 CurrentReg = 0x04,
63 ControlReg = 0x08,
64 IntClear = 0x0C,
65 RawISR = 0x10,
66 MaskedISR = 0x14,
67 BGLoad = 0x18,
68 Size = 0x20
69 };
70
71 BitUnion32(CTRL)
72 Bitfield<0> oneShot;
73 Bitfield<1> timerSize;
74 Bitfield<3,2> timerPrescale;
75 Bitfield<5> intEnable;
76 Bitfield<6> timerMode;
77 Bitfield<7> timerEnable;
78 EndBitUnion(CTRL)
79
80 protected:
81 std::string _name;
82
83 /** Pointer to parent class */
84 Sp804 *parent;
85
86 /** Number of interrupt to cause/clear */
87 uint32_t intNum;
88
89 /** Number of ticks in a clock input */
90 Tick clock;
91
92 /** Control register as specified above */
93 CTRL control;
94
95 /** If timer has caused an interrupt. This is irrespective of
96 * interrupt enable */
97 bool rawInt;
98
99 /** If an interrupt is currently pending. Logical and of CTRL.intEnable
100 * and rawInt */
101 bool pendingInt;
102
103 /** Value to load into counter when periodic mode reaches 0 */
104 uint32_t loadValue;
105
106 /** Called when the counter reaches 0 */
107 void counterAtZero();
108 EventWrapper<Timer, &Timer::counterAtZero> zeroEvent;
109
110 public:
111 /** Restart the counter ticking at val
112 * @param val the value to start at (pre-16 bit masking if en) */
113 void restartCounter(uint32_t val);
114
115 Timer(std::string __name, Sp804 *parent, int int_num, Tick clock);
116
117 std::string name() const { return _name; }
118
119 /** Handle read for a single timer */
120 void read(PacketPtr pkt, Addr daddr);
121
122 /** Handle write for a single timer */
123 void write(PacketPtr pkt, Addr daddr);
124
125 void serialize(std::ostream &os);
126 void unserialize(Checkpoint *cp, const std::string &section);
127
128 };
129
130 /** Pointer to the GIC for causing an interrupt */
131 Gic *gic;
132
133 /** Timers that do the actual work */
134 Timer timer0;
135 Timer timer1;
136
137 public:
138 typedef Sp804Params Params;
139 const Params *
140 params() const
141 {
142 return dynamic_cast<const Params *>(_params);
143 }
144 /**
145 * The constructor for RealView just registers itself with the MMU.
146 * @param p params structure
147 */
148 Sp804(Params *p);
149
150 /**
151 * Handle a read to the device
152 * @param pkt The memory request.
153 * @param data Where to put the data.
154 */
155 virtual Tick read(PacketPtr pkt);
156
157 /**
158 * All writes are simply ignored.
159 * @param pkt The memory request.
160 * @param data the data
161 */
162 virtual Tick write(PacketPtr pkt);
163
164
165 virtual void serialize(std::ostream &os);
166 virtual void unserialize(Checkpoint *cp, const std::string &section);
167};
168
169
170#endif // __DEV_ARM_SP804_HH__
171