timer_sp804.cc (12772:362544959c40) timer_sp804.cc (13230:2988dc5d1d6f)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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81}
82
83
84void
85Sp804::Timer::read(PacketPtr pkt, Addr daddr)
86{
87 switch(daddr) {
88 case LoadReg:
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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81}
82
83
84void
85Sp804::Timer::read(PacketPtr pkt, Addr daddr)
86{
87 switch(daddr) {
88 case LoadReg:
89 pkt->set(loadValue);
89 pkt->setLE<uint32_t>(loadValue);
90 break;
91 case CurrentReg:
92 DPRINTF(Timer, "Event schedule for %d, clock=%d, prescale=%d\n",
93 zeroEvent.when(), clock, control.timerPrescale);
94 Tick time;
95 time = zeroEvent.when() - curTick();
96 time = time / clock / power(16, control.timerPrescale);
97 DPRINTF(Timer, "-- returning counter at %d\n", time);
90 break;
91 case CurrentReg:
92 DPRINTF(Timer, "Event schedule for %d, clock=%d, prescale=%d\n",
93 zeroEvent.when(), clock, control.timerPrescale);
94 Tick time;
95 time = zeroEvent.when() - curTick();
96 time = time / clock / power(16, control.timerPrescale);
97 DPRINTF(Timer, "-- returning counter at %d\n", time);
98 pkt->set(time);
98 pkt->setLE<uint32_t>(time);
99 break;
100 case ControlReg:
99 break;
100 case ControlReg:
101 pkt->set(control);
101 pkt->setLE<uint32_t>(control);
102 break;
103 case RawISR:
102 break;
103 case RawISR:
104 pkt->set(rawInt);
104 pkt->setLE<uint32_t>(rawInt);
105 break;
106 case MaskedISR:
105 break;
106 case MaskedISR:
107 pkt->set(pendingInt);
107 pkt->setLE<uint32_t>(pendingInt);
108 break;
109 case BGLoad:
108 break;
109 case BGLoad:
110 pkt->set(loadValue);
110 pkt->setLE<uint32_t>(loadValue);
111 break;
112 default:
113 panic("Tried to read SP804 timer at offset %#x\n", daddr);
114 break;
115 }
111 break;
112 default:
113 panic("Tried to read SP804 timer at offset %#x\n", daddr);
114 break;
115 }
116 DPRINTF(Timer, "Reading %#x from Timer at offset: %#x\n", pkt->get<uint32_t>(), daddr);
116 DPRINTF(Timer, "Reading %#x from Timer at offset: %#x\n",
117 pkt->getLE<uint32_t>(), daddr);
117}
118
119Tick
120Sp804::write(PacketPtr pkt)
121{
122 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
123 assert(pkt->getSize() == 4);
124 Addr daddr = pkt->getAddr() - pioAddr;

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132 panic("Tried to write SP804 at offset %#x that doesn't exist\n", daddr);
133 pkt->makeAtomicResponse();
134 return pioDelay;
135}
136
137void
138Sp804::Timer::write(PacketPtr pkt, Addr daddr)
139{
118}
119
120Tick
121Sp804::write(PacketPtr pkt)
122{
123 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
124 assert(pkt->getSize() == 4);
125 Addr daddr = pkt->getAddr() - pioAddr;

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133 panic("Tried to write SP804 at offset %#x that doesn't exist\n", daddr);
134 pkt->makeAtomicResponse();
135 return pioDelay;
136}
137
138void
139Sp804::Timer::write(PacketPtr pkt, Addr daddr)
140{
140 DPRINTF(Timer, "Writing %#x to Timer at offset: %#x\n", pkt->get<uint32_t>(), daddr);
141 DPRINTF(Timer, "Writing %#x to Timer at offset: %#x\n",
142 pkt->getLE<uint32_t>(), daddr);
141 switch (daddr) {
142 case LoadReg:
143 switch (daddr) {
144 case LoadReg:
143 loadValue = pkt->get();
145 loadValue = pkt->getLE<uint32_t>();
144 restartCounter(loadValue);
145 break;
146 case CurrentReg:
147 // Spec says this value can't be written, but linux writes it anyway
148 break;
149 case ControlReg:
150 bool old_enable;
151 old_enable = control.timerEnable;
146 restartCounter(loadValue);
147 break;
148 case CurrentReg:
149 // Spec says this value can't be written, but linux writes it anyway
150 break;
151 case ControlReg:
152 bool old_enable;
153 old_enable = control.timerEnable;
152 control = pkt->get();
154 control = pkt->getLE<uint32_t>();
153 if ((old_enable == 0) && control.timerEnable)
154 restartCounter(loadValue);
155 break;
156 case IntClear:
157 rawInt = false;
158 if (pendingInt) {
159 pendingInt = false;
160 DPRINTF(Timer, "Clearing interrupt\n");
161 parent->gic->clearInt(intNum);
162 }
163 break;
164 case BGLoad:
155 if ((old_enable == 0) && control.timerEnable)
156 restartCounter(loadValue);
157 break;
158 case IntClear:
159 rawInt = false;
160 if (pendingInt) {
161 pendingInt = false;
162 DPRINTF(Timer, "Clearing interrupt\n");
163 parent->gic->clearInt(intNum);
164 }
165 break;
166 case BGLoad:
165 loadValue = pkt->get();
167 loadValue = pkt->getLE<uint32_t>();
166 break;
167 default:
168 panic("Tried to write SP804 timer at offset %#x\n", daddr);
169 break;
170 }
171}
172
173void

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169 default:
170 panic("Tried to write SP804 timer at offset %#x\n", daddr);
171 break;
172 }
173}
174
175void

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