timer_sp804.cc (8245:a9d06c894afe) | timer_sp804.cc (8524:1ddd1aa0e55b) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 71 unchanged lines hidden (view full) --- 80 pkt->makeAtomicResponse(); 81 return pioDelay; 82} 83 84 85void 86Sp804::Timer::read(PacketPtr pkt, Addr daddr) 87{ | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 71 unchanged lines hidden (view full) --- 80 pkt->makeAtomicResponse(); 81 return pioDelay; 82} 83 84 85void 86Sp804::Timer::read(PacketPtr pkt, Addr daddr) 87{ |
88 DPRINTF(Timer, "Reading from Timer at offset: %#x\n", daddr); 89 | |
90 switch(daddr) { 91 case LoadReg: 92 pkt->set<uint32_t>(loadValue); 93 break; 94 case CurrentReg: 95 DPRINTF(Timer, "Event schedule for %d, clock=%d, prescale=%d\n", 96 zeroEvent.when(), clock, control.timerPrescale); 97 Tick time; --- 13 unchanged lines hidden (view full) --- 111 break; 112 case BGLoad: 113 pkt->set<uint32_t>(loadValue); 114 break; 115 default: 116 panic("Tried to read SP804 timer at offset %#x\n", daddr); 117 break; 118 } | 88 switch(daddr) { 89 case LoadReg: 90 pkt->set<uint32_t>(loadValue); 91 break; 92 case CurrentReg: 93 DPRINTF(Timer, "Event schedule for %d, clock=%d, prescale=%d\n", 94 zeroEvent.when(), clock, control.timerPrescale); 95 Tick time; --- 13 unchanged lines hidden (view full) --- 109 break; 110 case BGLoad: 111 pkt->set<uint32_t>(loadValue); 112 break; 113 default: 114 panic("Tried to read SP804 timer at offset %#x\n", daddr); 115 break; 116 } |
117 DPRINTF(Timer, "Reading %#x from Timer at offset: %#x\n", pkt->get<uint32_t>(), daddr); |
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119} 120 121Tick 122Sp804::write(PacketPtr pkt) 123{ 124 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 125 assert(pkt->getSize() == 4); 126 Addr daddr = pkt->getAddr() - pioAddr; --- 8 unchanged lines hidden (view full) --- 135 panic("Tried to write SP804 at offset %#x that doesn't exist\n", daddr); 136 pkt->makeAtomicResponse(); 137 return pioDelay; 138} 139 140void 141Sp804::Timer::write(PacketPtr pkt, Addr daddr) 142{ | 118} 119 120Tick 121Sp804::write(PacketPtr pkt) 122{ 123 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 124 assert(pkt->getSize() == 4); 125 Addr daddr = pkt->getAddr() - pioAddr; --- 8 unchanged lines hidden (view full) --- 134 panic("Tried to write SP804 at offset %#x that doesn't exist\n", daddr); 135 pkt->makeAtomicResponse(); 136 return pioDelay; 137} 138 139void 140Sp804::Timer::write(PacketPtr pkt, Addr daddr) 141{ |
143 DPRINTF(Timer, "Writing to Timer at offset: %#x\n", daddr); | 142 DPRINTF(Timer, "Writing %#x to Timer at offset: %#x\n", pkt->get<uint32_t>(), daddr); |
144 switch (daddr) { 145 case LoadReg: 146 loadValue = pkt->get<uint32_t>(); 147 restartCounter(loadValue); 148 break; 149 case CurrentReg: 150 // Spec says this value can't be written, but linux writes it anyway 151 break; --- 145 unchanged lines hidden --- | 143 switch (daddr) { 144 case LoadReg: 145 loadValue = pkt->get<uint32_t>(); 146 restartCounter(loadValue); 147 break; 148 case CurrentReg: 149 // Spec says this value can't be written, but linux writes it anyway 150 break; --- 145 unchanged lines hidden --- |