timer_cpulocal.hh (9545:508784fad4e5) timer_cpulocal.hh (10905:a6ca6831e775)
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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50 * Technical Reference Manual rev r2p2 (ARM DDI 0407F)
51 */
52
53class BaseGic;
54
55class CpuLocalTimer : public BasicPioDevice
56{
57 protected:
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 41 unchanged lines hidden (view full) ---

50 * Technical Reference Manual rev r2p2 (ARM DDI 0407F)
51 */
52
53class BaseGic;
54
55class CpuLocalTimer : public BasicPioDevice
56{
57 protected:
58 class Timer
58 class Timer : public Serializable
59 {
60
61 public:
62 enum {
63 TimerLoadReg = 0x00,
64 TimerCounterReg = 0x04,
65 TimerControlReg = 0x08,
66 TimerIntStatusReg = 0x0C,

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140 std::string name() const { return _name; }
141
142 /** Handle read for a single timer */
143 void read(PacketPtr pkt, Addr daddr);
144
145 /** Handle write for a single timer */
146 void write(PacketPtr pkt, Addr daddr);
147
59 {
60
61 public:
62 enum {
63 TimerLoadReg = 0x00,
64 TimerCounterReg = 0x04,
65 TimerControlReg = 0x08,
66 TimerIntStatusReg = 0x0C,

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140 std::string name() const { return _name; }
141
142 /** Handle read for a single timer */
143 void read(PacketPtr pkt, Addr daddr);
144
145 /** Handle write for a single timer */
146 void write(PacketPtr pkt, Addr daddr);
147
148 void serialize(std::ostream &os);
149 void unserialize(Checkpoint *cp, const std::string &section);
148 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
149 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
150
151 friend class CpuLocalTimer;
152 };
153
154 static const int CPU_MAX = 8;
155
156 /** Pointer to the GIC for causing an interrupt */
157 BaseGic *gic;

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181
182 /**
183 * Handle a write to the device.
184 * @param pkt The memory request.
185 * @return Returns latency of device write
186 */
187 virtual Tick write(PacketPtr pkt);
188
150
151 friend class CpuLocalTimer;
152 };
153
154 static const int CPU_MAX = 8;
155
156 /** Pointer to the GIC for causing an interrupt */
157 BaseGic *gic;

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181
182 /**
183 * Handle a write to the device.
184 * @param pkt The memory request.
185 * @return Returns latency of device write
186 */
187 virtual Tick write(PacketPtr pkt);
188
189
190 virtual void serialize(std::ostream &os);
191 virtual void unserialize(Checkpoint *cp, const std::string &section);
189 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
190 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
192};
193
194
195#endif // __DEV_ARM_SP804_HH__
196
191};
192
193
194#endif // __DEV_ARM_SP804_HH__
195