1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 * Geoffrey Blake
39 */
40
41#include "base/intmath.hh"
42#include "base/trace.hh"
43#include "debug/Checkpoint.hh"
44#include "debug/Timer.hh"
45#include "dev/arm/base_gic.hh"
46#include "dev/arm/timer_cpulocal.hh"
47#include "mem/packet.hh"
48#include "mem/packet_access.hh"
49
50CpuLocalTimer::CpuLocalTimer(Params *p)
51 : BasicPioDevice(p, 0x38), gic(p->gic)
52{
53 // Initialize the timer registers for each per cpu timer
54 for (int i = 0; i < CPU_MAX; i++) {
55 std::stringstream oss;
56 oss << name() << ".timer" << i;
57 localTimer[i]._name = oss.str();
58 localTimer[i].parent = this;
59 localTimer[i].intNumTimer = p->int_num_timer;
60 localTimer[i].intNumWatchdog = p->int_num_watchdog;
61 localTimer[i].cpuNum = i;
62 }
63}
64
65CpuLocalTimer::Timer::Timer()
66 : timerControl(0x0), watchdogControl(0x0), rawIntTimer(false), rawIntWatchdog(false),
67 rawResetWatchdog(false), watchdogDisableReg(0x0), pendingIntTimer(false), pendingIntWatchdog(false),
68 timerLoadValue(0x0), watchdogLoadValue(0x0), timerZeroEvent(this), watchdogZeroEvent(this)
69{
70}
71
72Tick
73CpuLocalTimer::read(PacketPtr pkt)
74{
75 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
76 assert(pkt->getSize() == 4);
77 Addr daddr = pkt->getAddr() - pioAddr;
78 int cpu_id = pkt->req->contextId();
79 DPRINTF(Timer, "Reading from CpuLocalTimer at offset: %#x\n", daddr);
80 assert(cpu_id >= 0);
81 assert(cpu_id < CPU_MAX);
82
83 if (daddr < Timer::Size)
84 localTimer[cpu_id].read(pkt, daddr);
85 else
86 panic("Tried to read CpuLocalTimer at offset %#x that doesn't exist\n", daddr);
87 pkt->makeAtomicResponse();
88 return pioDelay;
89}
90
91
92void
93CpuLocalTimer::Timer::read(PacketPtr pkt, Addr daddr)
94{
95 DPRINTF(Timer, "Reading from CpuLocalTimer at offset: %#x\n", daddr);
96 Tick time;
97
98 switch(daddr) {
99 case TimerLoadReg:
100 pkt->set<uint32_t>(timerLoadValue);
101 break;
102 case TimerCounterReg:
103 DPRINTF(Timer, "Event schedule for timer %d, clock=%d, prescale=%d\n",
104 timerZeroEvent.when(), parent->clockPeriod(),
105 timerControl.prescalar);
106 time = timerZeroEvent.when() - curTick();
107 time = time / parent->clockPeriod() /
108 power(16, timerControl.prescalar);
109 DPRINTF(Timer, "-- returning counter at %d\n", time);
110 pkt->set<uint32_t>(time);
111 break;
112 case TimerControlReg:
113 pkt->set<uint32_t>(timerControl);
114 break;
115 case TimerIntStatusReg:
116 pkt->set<uint32_t>(rawIntTimer);
117 break;
118 case WatchdogLoadReg:
119 pkt->set<uint32_t>(watchdogLoadValue);
120 break;
121 case WatchdogCounterReg:
122 DPRINTF(Timer,
123 "Event schedule for watchdog %d, clock=%d, prescale=%d\n",
124 watchdogZeroEvent.when(), parent->clockPeriod(),
125 watchdogControl.prescalar);
126 time = watchdogZeroEvent.when() - curTick();
127 time = time / parent->clockPeriod() /
128 power(16, watchdogControl.prescalar);
129 DPRINTF(Timer, "-- returning counter at %d\n", time);
130 pkt->set<uint32_t>(time);
131 break;
132 case WatchdogControlReg:
133 pkt->set<uint32_t>(watchdogControl);
134 break;
135 case WatchdogIntStatusReg:
136 pkt->set<uint32_t>(rawIntWatchdog);
137 break;
138 case WatchdogResetStatusReg:
139 pkt->set<uint32_t>(rawResetWatchdog);
140 break;
141 case WatchdogDisableReg:
142 panic("Tried to read from WatchdogDisableRegister\n");
143 break;
144 default:
145 panic("Tried to read CpuLocalTimer at offset %#x\n", daddr);
146 break;
147 }
148}
149
150Tick
151CpuLocalTimer::write(PacketPtr pkt)
152{
153 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
154 assert(pkt->getSize() == 4);
155 Addr daddr = pkt->getAddr() - pioAddr;
156 int cpu_id = pkt->req->contextId();
157 DPRINTF(Timer, "Writing to CpuLocalTimer at offset: %#x\n", daddr);
158 assert(cpu_id >= 0);
159 assert(cpu_id < CPU_MAX);
160
161 if (daddr < Timer::Size)
162 localTimer[cpu_id].write(pkt, daddr);
163 else
164 panic("Tried to write CpuLocalTimer at offset %#x that doesn't exist\n", daddr);
165 pkt->makeAtomicResponse();
166 return pioDelay;
167}
168
169void
170CpuLocalTimer::Timer::write(PacketPtr pkt, Addr daddr)
171{
172 DPRINTF(Timer, "Writing to CpuLocalTimer at offset: %#x\n", daddr);
173 bool old_enable;
174 bool old_wd_mode;
175 uint32_t old_val;
176
177 switch (daddr) {
178 case TimerLoadReg:
179 // Writing to this register also resets the counter register and
180 // starts decrementing if the counter is enabled.
181 timerLoadValue = pkt->get<uint32_t>();
182 restartTimerCounter(timerLoadValue);
183 break;
184 case TimerCounterReg:
185 // Can be written, doesn't start counting unless the timer is enabled
186 restartTimerCounter(pkt->get<uint32_t>());
187 break;
188 case TimerControlReg:
189 old_enable = timerControl.enable;
190 timerControl = pkt->get<uint32_t>();
191 if ((old_enable == 0) && timerControl.enable)
192 restartTimerCounter(timerLoadValue);
193 break;
194 case TimerIntStatusReg:
195 rawIntTimer = false;
196 if (pendingIntTimer) {
197 pendingIntTimer = false;
198 DPRINTF(Timer, "Clearing interrupt\n");
199 }
200 break;
201 case WatchdogLoadReg:
202 watchdogLoadValue = pkt->get<uint32_t>();
203 restartWatchdogCounter(watchdogLoadValue);
204 break;
205 case WatchdogCounterReg:
206 // Can't be written when in watchdog mode, but can in timer mode
207 if (!watchdogControl.watchdogMode) {
208 restartWatchdogCounter(pkt->get<uint32_t>());
209 }
210 break;
211 case WatchdogControlReg:
212 old_enable = watchdogControl.enable;
213 old_wd_mode = watchdogControl.watchdogMode;
214 watchdogControl = pkt->get<uint32_t>();
215 if ((old_enable == 0) && watchdogControl.enable)
216 restartWatchdogCounter(watchdogLoadValue);
217 // cannot disable watchdog using control register
218 if ((old_wd_mode == 1) && watchdogControl.watchdogMode == 0)
219 watchdogControl.watchdogMode = 1;
220 break;
221 case WatchdogIntStatusReg:
222 rawIntWatchdog = false;
223 if (pendingIntWatchdog) {
224 pendingIntWatchdog = false;
225 DPRINTF(Timer, "Clearing watchdog interrupt\n");
226 }
227 break;
228 case WatchdogResetStatusReg:
229 rawResetWatchdog = false;
230 DPRINTF(Timer, "Clearing watchdog reset flag\n");
231 break;
232 case WatchdogDisableReg:
233 old_val = watchdogDisableReg;
234 watchdogDisableReg = pkt->get<uint32_t>();
235 // if this sequence is observed, turn off watchdog mode
236 if (old_val == 0x12345678 && watchdogDisableReg == 0x87654321)
237 watchdogControl.watchdogMode = 0;
238 break;
239 default:
240 panic("Tried to write CpuLocalTimer timer at offset %#x\n", daddr);
241 break;
242 }
243}
244
245//XXX: Two functions are needed because the control registers are different types
246void
247CpuLocalTimer::Timer::restartTimerCounter(uint32_t val)
248{
249 DPRINTF(Timer, "Resetting timer counter with value %#x\n", val);
250 if (!timerControl.enable)
251 return;
252
253 Tick time = parent->clockPeriod() * power(16, timerControl.prescalar);
254 time *= val;
255
256 if (timerZeroEvent.scheduled()) {
257 DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n");
258 parent->deschedule(timerZeroEvent);
259 }
260 parent->schedule(timerZeroEvent, curTick() + time);
261 DPRINTF(Timer, "-- Scheduling new event for: %d\n", curTick() + time);
262}
263
264void
265CpuLocalTimer::Timer::restartWatchdogCounter(uint32_t val)
266{
267 DPRINTF(Timer, "Resetting watchdog counter with value %#x\n", val);
268 if (!watchdogControl.enable)
269 return;
270
271 Tick time = parent->clockPeriod() * power(16, watchdogControl.prescalar);
272 time *= val;
273
274 if (watchdogZeroEvent.scheduled()) {
275 DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n");
276 parent->deschedule(watchdogZeroEvent);
277 }
278 parent->schedule(watchdogZeroEvent, curTick() + time);
279 DPRINTF(Timer, "-- Scheduling new event for: %d\n", curTick() + time);
280}
281//////
282
283void
284CpuLocalTimer::Timer::timerAtZero()
285{
286 if (!timerControl.enable)
287 return;
288
289 DPRINTF(Timer, "Timer Counter reached zero\n");
290
291 rawIntTimer = true;
292 bool old_pending = pendingIntTimer;
293 if (timerControl.intEnable)
294 pendingIntTimer = true;
295 if (pendingIntTimer && !old_pending) {
296 DPRINTF(Timer, "-- Causing interrupt\n");
297 parent->gic->sendPPInt(intNumTimer, cpuNum);
298 }
299
300 if (!timerControl.autoReload)
301 return;
302 else
303 restartTimerCounter(timerLoadValue);
304}
305
306void
307CpuLocalTimer::Timer::watchdogAtZero()
308{
309 if (!watchdogControl.enable)
310 return;
311
312 DPRINTF(Timer, "Watchdog Counter reached zero\n");
313
314 rawIntWatchdog = true;
315 bool old_pending = pendingIntWatchdog;
316 // generates an interrupt only if the watchdog is in timer
317 // mode.
318 if (watchdogControl.intEnable && !watchdogControl.watchdogMode)
319 pendingIntWatchdog = true;
320 else if (watchdogControl.watchdogMode) {
321 rawResetWatchdog = true;
322 fatal("gem5 ARM Model does not support true watchdog operation!\n");
323 //XXX: Should we ever support a true watchdog reset?
324 }
325
326 if (pendingIntWatchdog && !old_pending) {
327 DPRINTF(Timer, "-- Causing interrupt\n");
328 parent->gic->sendPPInt(intNumWatchdog, cpuNum);
329 }
330
331 if (watchdogControl.watchdogMode)
332 return;
333 else if (watchdogControl.autoReload)
334 restartWatchdogCounter(watchdogLoadValue);
335}
336
337void
| 1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 * Geoffrey Blake
39 */
40
41#include "base/intmath.hh"
42#include "base/trace.hh"
43#include "debug/Checkpoint.hh"
44#include "debug/Timer.hh"
45#include "dev/arm/base_gic.hh"
46#include "dev/arm/timer_cpulocal.hh"
47#include "mem/packet.hh"
48#include "mem/packet_access.hh"
49
50CpuLocalTimer::CpuLocalTimer(Params *p)
51 : BasicPioDevice(p, 0x38), gic(p->gic)
52{
53 // Initialize the timer registers for each per cpu timer
54 for (int i = 0; i < CPU_MAX; i++) {
55 std::stringstream oss;
56 oss << name() << ".timer" << i;
57 localTimer[i]._name = oss.str();
58 localTimer[i].parent = this;
59 localTimer[i].intNumTimer = p->int_num_timer;
60 localTimer[i].intNumWatchdog = p->int_num_watchdog;
61 localTimer[i].cpuNum = i;
62 }
63}
64
65CpuLocalTimer::Timer::Timer()
66 : timerControl(0x0), watchdogControl(0x0), rawIntTimer(false), rawIntWatchdog(false),
67 rawResetWatchdog(false), watchdogDisableReg(0x0), pendingIntTimer(false), pendingIntWatchdog(false),
68 timerLoadValue(0x0), watchdogLoadValue(0x0), timerZeroEvent(this), watchdogZeroEvent(this)
69{
70}
71
72Tick
73CpuLocalTimer::read(PacketPtr pkt)
74{
75 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
76 assert(pkt->getSize() == 4);
77 Addr daddr = pkt->getAddr() - pioAddr;
78 int cpu_id = pkt->req->contextId();
79 DPRINTF(Timer, "Reading from CpuLocalTimer at offset: %#x\n", daddr);
80 assert(cpu_id >= 0);
81 assert(cpu_id < CPU_MAX);
82
83 if (daddr < Timer::Size)
84 localTimer[cpu_id].read(pkt, daddr);
85 else
86 panic("Tried to read CpuLocalTimer at offset %#x that doesn't exist\n", daddr);
87 pkt->makeAtomicResponse();
88 return pioDelay;
89}
90
91
92void
93CpuLocalTimer::Timer::read(PacketPtr pkt, Addr daddr)
94{
95 DPRINTF(Timer, "Reading from CpuLocalTimer at offset: %#x\n", daddr);
96 Tick time;
97
98 switch(daddr) {
99 case TimerLoadReg:
100 pkt->set<uint32_t>(timerLoadValue);
101 break;
102 case TimerCounterReg:
103 DPRINTF(Timer, "Event schedule for timer %d, clock=%d, prescale=%d\n",
104 timerZeroEvent.when(), parent->clockPeriod(),
105 timerControl.prescalar);
106 time = timerZeroEvent.when() - curTick();
107 time = time / parent->clockPeriod() /
108 power(16, timerControl.prescalar);
109 DPRINTF(Timer, "-- returning counter at %d\n", time);
110 pkt->set<uint32_t>(time);
111 break;
112 case TimerControlReg:
113 pkt->set<uint32_t>(timerControl);
114 break;
115 case TimerIntStatusReg:
116 pkt->set<uint32_t>(rawIntTimer);
117 break;
118 case WatchdogLoadReg:
119 pkt->set<uint32_t>(watchdogLoadValue);
120 break;
121 case WatchdogCounterReg:
122 DPRINTF(Timer,
123 "Event schedule for watchdog %d, clock=%d, prescale=%d\n",
124 watchdogZeroEvent.when(), parent->clockPeriod(),
125 watchdogControl.prescalar);
126 time = watchdogZeroEvent.when() - curTick();
127 time = time / parent->clockPeriod() /
128 power(16, watchdogControl.prescalar);
129 DPRINTF(Timer, "-- returning counter at %d\n", time);
130 pkt->set<uint32_t>(time);
131 break;
132 case WatchdogControlReg:
133 pkt->set<uint32_t>(watchdogControl);
134 break;
135 case WatchdogIntStatusReg:
136 pkt->set<uint32_t>(rawIntWatchdog);
137 break;
138 case WatchdogResetStatusReg:
139 pkt->set<uint32_t>(rawResetWatchdog);
140 break;
141 case WatchdogDisableReg:
142 panic("Tried to read from WatchdogDisableRegister\n");
143 break;
144 default:
145 panic("Tried to read CpuLocalTimer at offset %#x\n", daddr);
146 break;
147 }
148}
149
150Tick
151CpuLocalTimer::write(PacketPtr pkt)
152{
153 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
154 assert(pkt->getSize() == 4);
155 Addr daddr = pkt->getAddr() - pioAddr;
156 int cpu_id = pkt->req->contextId();
157 DPRINTF(Timer, "Writing to CpuLocalTimer at offset: %#x\n", daddr);
158 assert(cpu_id >= 0);
159 assert(cpu_id < CPU_MAX);
160
161 if (daddr < Timer::Size)
162 localTimer[cpu_id].write(pkt, daddr);
163 else
164 panic("Tried to write CpuLocalTimer at offset %#x that doesn't exist\n", daddr);
165 pkt->makeAtomicResponse();
166 return pioDelay;
167}
168
169void
170CpuLocalTimer::Timer::write(PacketPtr pkt, Addr daddr)
171{
172 DPRINTF(Timer, "Writing to CpuLocalTimer at offset: %#x\n", daddr);
173 bool old_enable;
174 bool old_wd_mode;
175 uint32_t old_val;
176
177 switch (daddr) {
178 case TimerLoadReg:
179 // Writing to this register also resets the counter register and
180 // starts decrementing if the counter is enabled.
181 timerLoadValue = pkt->get<uint32_t>();
182 restartTimerCounter(timerLoadValue);
183 break;
184 case TimerCounterReg:
185 // Can be written, doesn't start counting unless the timer is enabled
186 restartTimerCounter(pkt->get<uint32_t>());
187 break;
188 case TimerControlReg:
189 old_enable = timerControl.enable;
190 timerControl = pkt->get<uint32_t>();
191 if ((old_enable == 0) && timerControl.enable)
192 restartTimerCounter(timerLoadValue);
193 break;
194 case TimerIntStatusReg:
195 rawIntTimer = false;
196 if (pendingIntTimer) {
197 pendingIntTimer = false;
198 DPRINTF(Timer, "Clearing interrupt\n");
199 }
200 break;
201 case WatchdogLoadReg:
202 watchdogLoadValue = pkt->get<uint32_t>();
203 restartWatchdogCounter(watchdogLoadValue);
204 break;
205 case WatchdogCounterReg:
206 // Can't be written when in watchdog mode, but can in timer mode
207 if (!watchdogControl.watchdogMode) {
208 restartWatchdogCounter(pkt->get<uint32_t>());
209 }
210 break;
211 case WatchdogControlReg:
212 old_enable = watchdogControl.enable;
213 old_wd_mode = watchdogControl.watchdogMode;
214 watchdogControl = pkt->get<uint32_t>();
215 if ((old_enable == 0) && watchdogControl.enable)
216 restartWatchdogCounter(watchdogLoadValue);
217 // cannot disable watchdog using control register
218 if ((old_wd_mode == 1) && watchdogControl.watchdogMode == 0)
219 watchdogControl.watchdogMode = 1;
220 break;
221 case WatchdogIntStatusReg:
222 rawIntWatchdog = false;
223 if (pendingIntWatchdog) {
224 pendingIntWatchdog = false;
225 DPRINTF(Timer, "Clearing watchdog interrupt\n");
226 }
227 break;
228 case WatchdogResetStatusReg:
229 rawResetWatchdog = false;
230 DPRINTF(Timer, "Clearing watchdog reset flag\n");
231 break;
232 case WatchdogDisableReg:
233 old_val = watchdogDisableReg;
234 watchdogDisableReg = pkt->get<uint32_t>();
235 // if this sequence is observed, turn off watchdog mode
236 if (old_val == 0x12345678 && watchdogDisableReg == 0x87654321)
237 watchdogControl.watchdogMode = 0;
238 break;
239 default:
240 panic("Tried to write CpuLocalTimer timer at offset %#x\n", daddr);
241 break;
242 }
243}
244
245//XXX: Two functions are needed because the control registers are different types
246void
247CpuLocalTimer::Timer::restartTimerCounter(uint32_t val)
248{
249 DPRINTF(Timer, "Resetting timer counter with value %#x\n", val);
250 if (!timerControl.enable)
251 return;
252
253 Tick time = parent->clockPeriod() * power(16, timerControl.prescalar);
254 time *= val;
255
256 if (timerZeroEvent.scheduled()) {
257 DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n");
258 parent->deschedule(timerZeroEvent);
259 }
260 parent->schedule(timerZeroEvent, curTick() + time);
261 DPRINTF(Timer, "-- Scheduling new event for: %d\n", curTick() + time);
262}
263
264void
265CpuLocalTimer::Timer::restartWatchdogCounter(uint32_t val)
266{
267 DPRINTF(Timer, "Resetting watchdog counter with value %#x\n", val);
268 if (!watchdogControl.enable)
269 return;
270
271 Tick time = parent->clockPeriod() * power(16, watchdogControl.prescalar);
272 time *= val;
273
274 if (watchdogZeroEvent.scheduled()) {
275 DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n");
276 parent->deschedule(watchdogZeroEvent);
277 }
278 parent->schedule(watchdogZeroEvent, curTick() + time);
279 DPRINTF(Timer, "-- Scheduling new event for: %d\n", curTick() + time);
280}
281//////
282
283void
284CpuLocalTimer::Timer::timerAtZero()
285{
286 if (!timerControl.enable)
287 return;
288
289 DPRINTF(Timer, "Timer Counter reached zero\n");
290
291 rawIntTimer = true;
292 bool old_pending = pendingIntTimer;
293 if (timerControl.intEnable)
294 pendingIntTimer = true;
295 if (pendingIntTimer && !old_pending) {
296 DPRINTF(Timer, "-- Causing interrupt\n");
297 parent->gic->sendPPInt(intNumTimer, cpuNum);
298 }
299
300 if (!timerControl.autoReload)
301 return;
302 else
303 restartTimerCounter(timerLoadValue);
304}
305
306void
307CpuLocalTimer::Timer::watchdogAtZero()
308{
309 if (!watchdogControl.enable)
310 return;
311
312 DPRINTF(Timer, "Watchdog Counter reached zero\n");
313
314 rawIntWatchdog = true;
315 bool old_pending = pendingIntWatchdog;
316 // generates an interrupt only if the watchdog is in timer
317 // mode.
318 if (watchdogControl.intEnable && !watchdogControl.watchdogMode)
319 pendingIntWatchdog = true;
320 else if (watchdogControl.watchdogMode) {
321 rawResetWatchdog = true;
322 fatal("gem5 ARM Model does not support true watchdog operation!\n");
323 //XXX: Should we ever support a true watchdog reset?
324 }
325
326 if (pendingIntWatchdog && !old_pending) {
327 DPRINTF(Timer, "-- Causing interrupt\n");
328 parent->gic->sendPPInt(intNumWatchdog, cpuNum);
329 }
330
331 if (watchdogControl.watchdogMode)
332 return;
333 else if (watchdogControl.autoReload)
334 restartWatchdogCounter(watchdogLoadValue);
335}
336
337void
|