1/* 2 * Copyright (c) 2013, 2018-2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Stan Czerniawski 38 */ 39 40#ifndef __DEV_ARM_SMMU_V3_TRANSL_HH__ 41#define __DEV_ARM_SMMU_V3_TRANSL_HH__ 42 43#include "dev/arm/smmu_v3_proc.hh" 44#include "dev/arm/smmu_v3_ptops.hh" 45#include "dev/arm/smmu_v3_slaveifc.hh" 46#include "mem/packet.hh" 47 48struct SMMUTranslRequest 49{ 50 Addr addr; 51 unsigned size; 52 uint32_t sid; // streamId 53 uint32_t ssid; // substreamId 54 bool isWrite; 55 bool isPrefetch; 56 bool isAtsRequest; 57 58 PacketPtr pkt; 59 60 static SMMUTranslRequest fromPacket(PacketPtr pkt, bool ats = false); 61 static SMMUTranslRequest prefetch(Addr addr, uint32_t sid, uint32_t ssid); 62}; 63 64class SMMUTranslationProcess : public SMMUProcess 65{ 66 private: 67 struct TranslContext 68 { 69 bool stage1Enable; 70 bool stage2Enable; 71 Addr ttb0, ttb1, httb; 72 uint16_t asid; 73 uint16_t vmid; 74 uint8_t stage1TranslGranule; 75 uint8_t stage2TranslGranule; 76 }; 77 78 enum FaultType 79 { 80 FAULT_NONE, 81 FAULT_TRANSLATION, // F_TRANSLATION 82 FAULT_PERMISSION, // F_PERMISSION 83 }; 84 85 struct TranslResult 86 { 87 FaultType fault; 88 Addr addr; 89 Addr addrMask; 90 bool writable; 91 }; 92 93 SMMUv3SlaveInterface &ifc; 94 95 SMMUTranslRequest request; 96 TranslContext context; 97 98 Tick recvTick; 99 Tick faultTick; 100 101 virtual void main(Yield &yield); 102 103 TranslResult bypass(Addr addr) const; 104 TranslResult smmuTranslation(Yield &yield); 105 106 bool microTLBLookup(Yield &yield, TranslResult &tr); 107 bool ifcTLBLookup(Yield &yield, TranslResult &tr, bool &wasPrefetched); 108 bool smmuTLBLookup(Yield &yield, TranslResult &tr); 109 110 void microTLBUpdate(Yield &yield, const TranslResult &tr); 111 void ifcTLBUpdate(Yield &yield, const TranslResult &tr); 112 void smmuTLBUpdate(Yield &yield, const TranslResult &tr); 113 114 bool configCacheLookup(Yield &yield, TranslContext &tc); 115 void configCacheUpdate(Yield &yield, const TranslContext &tc); 116 bool findConfig(Yield &yield, TranslContext &tc, TranslResult &tr); 117 118 void walkCacheLookup(Yield &yield, 119 const WalkCache::Entry *&walkEntry, 120 Addr addr, uint16_t asid, uint16_t vmid, 121 unsigned stage, unsigned level); 122 123 void walkCacheUpdate(Yield &yield, Addr va, Addr vaMask, Addr pa, 124 unsigned stage, unsigned level, 125 bool leaf, uint8_t permissions); 126 127 TranslResult walkStage1And2(Yield &yield, Addr addr, 128 const PageTableOps *pt_ops, 129 unsigned level, Addr walkPtr); 130 131 TranslResult walkStage2(Yield &yield, Addr addr, bool final_tr, 132 const PageTableOps *pt_ops, 133 unsigned level, Addr walkPtr); 134 135 TranslResult translateStage1And2(Yield &yield, Addr addr); 136 TranslResult translateStage2(Yield &yield, Addr addr, bool final_tr); 137 138 TranslResult combineTranslations(const TranslResult &s1tr, 139 const TranslResult &s2tr) const; 140 141 /** 142 * Used to force ordering on transactions with same 143 * (SID, SSID, 4k page) to avoid multiple identical 144 * page-table walks. 145 */ 146 bool hazard4kCheck(); 147 void hazard4kRegister(); 148 void hazard4kHold(Yield &yield); 149 void hazard4kRelease(); 150 151 /** 152 * Used to force ordering on transactions with the same orderId. 153 * This attempts to model AXI IDs. 154 */ 155 void hazardIdRegister(); 156 void hazardIdHold(Yield &yield); 157 void hazardIdRelease(); 158 159 void issuePrefetch(Addr addr); 160 161 void completeTransaction(Yield &yield, const TranslResult &tr); 162 void completePrefetch(Yield &yield); 163 164 void sendEvent(Yield &yield, const SMMUEvent &ev); 165 166 void doReadSTE(Yield &yield, StreamTableEntry &ste, uint32_t sid); 167 void doReadCD(Yield &yield, ContextDescriptor &cd, 168 const StreamTableEntry &ste, uint32_t sid, uint32_t ssid); 169 void doReadConfig(Yield &yield, Addr addr, void *ptr, size_t size, 170 uint32_t sid, uint32_t ssid); 171 void doReadPTE(Yield &yield, Addr va, Addr addr, void *ptr, 172 unsigned stage, unsigned level); 173 174 public: 175 SMMUTranslationProcess(const std::string &name, SMMUv3 &_smmu,
|