smmu_v3_transl.cc (14102:b0b52ccb7e1b) smmu_v3_transl.cc (14223:ae17e22dcae5)
1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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82 SMMUv3 &_smmu, SMMUv3SlaveInterface &_ifc)
83 :
84 SMMUProcess(name, _smmu),
85 ifc(_ifc)
86{
87 // Decrease number of pending translation slots on the slave interface
88 assert(ifc.xlateSlotsRemaining > 0);
89 ifc.xlateSlotsRemaining--;
1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 73 unchanged lines hidden (view full) ---

82 SMMUv3 &_smmu, SMMUv3SlaveInterface &_ifc)
83 :
84 SMMUProcess(name, _smmu),
85 ifc(_ifc)
86{
87 // Decrease number of pending translation slots on the slave interface
88 assert(ifc.xlateSlotsRemaining > 0);
89 ifc.xlateSlotsRemaining--;
90
91 ifc.pendingMemAccesses++;
90 reinit();
91}
92
93SMMUTranslationProcess::~SMMUTranslationProcess()
94{
95 // Increase number of pending translation slots on the slave interface
92 reinit();
93}
94
95SMMUTranslationProcess::~SMMUTranslationProcess()
96{
97 // Increase number of pending translation slots on the slave interface
96 ifc.xlateSlotsRemaining++;
97 // If no more SMMU translations are pending (all slots available),
98 assert(ifc.pendingMemAccesses > 0);
99 ifc.pendingMemAccesses--;
100
101 // If no more SMMU memory accesses are pending,
98 // signal SMMU Slave Interface as drained
102 // signal SMMU Slave Interface as drained
99 if (ifc.xlateSlotsRemaining == ifc.params()->xlate_slots) {
103 if (ifc.pendingMemAccesses == 0) {
100 ifc.signalDrainDone();
101 }
102}
103
104void
105SMMUTranslationProcess::beginTransaction(const SMMUTranslRequest &req)
106{
107 request = req;

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1227 1;
1228
1229 doSemaphoreDown(yield, smmu.masterPortSem);
1230 doDelay(yield, Cycles(numMasterBeats));
1231 doSemaphoreUp(smmu.masterPortSem);
1232
1233
1234 smmu.translationTimeDist.sample(curTick() - recvTick);
104 ifc.signalDrainDone();
105 }
106}
107
108void
109SMMUTranslationProcess::beginTransaction(const SMMUTranslRequest &req)
110{
111 request = req;

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1231 1;
1232
1233 doSemaphoreDown(yield, smmu.masterPortSem);
1234 doDelay(yield, Cycles(numMasterBeats));
1235 doSemaphoreUp(smmu.masterPortSem);
1236
1237
1238 smmu.translationTimeDist.sample(curTick() - recvTick);
1239 ifc.xlateSlotsRemaining++;
1235 if (!request.isAtsRequest && request.isWrite)
1236 ifc.wrBufSlotsRemaining +=
1237 (request.size + (ifc.portWidth-1)) / ifc.portWidth;
1238
1239 smmu.scheduleSlaveRetries();
1240
1241
1242 SMMUAction a;

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1274 a.delay = 0;
1275 yield(a);
1276 }
1277}
1278
1279void
1280SMMUTranslationProcess::completePrefetch(Yield &yield)
1281{
1240 if (!request.isAtsRequest && request.isWrite)
1241 ifc.wrBufSlotsRemaining +=
1242 (request.size + (ifc.portWidth-1)) / ifc.portWidth;
1243
1244 smmu.scheduleSlaveRetries();
1245
1246
1247 SMMUAction a;

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1279 a.delay = 0;
1280 yield(a);
1281 }
1282}
1283
1284void
1285SMMUTranslationProcess::completePrefetch(Yield &yield)
1286{
1287 ifc.xlateSlotsRemaining++;
1288
1282 SMMUAction a;
1283 a.type = ACTION_TERMINATE;
1284 a.pkt = NULL;
1285 a.ifc = &ifc;
1286 a.delay = 0;
1287 yield(a);
1288}
1289

--- 181 unchanged lines hidden --- 		1289 SMMUAction a;
1290 a.type = ACTION_TERMINATE;
1291 a.pkt = NULL;
1292 a.ifc = &ifc;
1293 a.delay = 0;
1294 yield(a);
1295}
1296

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